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Hi, Kriz
You can refer the Microelectronics Circuit by Sedra and Smith in which you can find out the Two stage CMOS opamp with PMOS differential input pair ( Chapter: Oparational Amplifier and Data Converter Circuit ). By the way It is quiet easy to find the ICMR range.
For Max input traverse...
Hi, I am using TSMC18rf and wanna do corner analysis in Cadence. I have given the path but I am somehow confused that within spectre which file contain model parameters information. I have gone through various link, some of them say add .pcf and .dcf file but I have seen only .pcf file but when...
Hi, I have designed an NGCC opamp with a bias voltage applied to gate of
Driver pmos of first stage diff. Amplifier as 52 mv. My question is in order to measure the offset voltage which of the following test bench is correct:
(1) as a voltage follower with 52 mv at non inverting terminal and...
Hi, Anhnha;
You can choose load capacitance on the basis of UGB required for this amplifier. Just find out the effective Gm of the amplifier then Gm/Cl is your UGB. Otherwise, if you know UGB and choose Cl according to your requirement then you can calculate the Gm.
See you can increase the...
Hi, I have designed an opamp of gain 120dB and ugb in the range of 2-3 MHz with power consumption nearly 0.5 mw and settling time is in the range of 200 ns with a single power supply of 1.2V.
I have a query that which area needed such an opamp specification........
I have read papers on high...
Hi, I am designing Opamp for Sub-Threshold region. I am designing first stage and when I have simulated it in cadence I found that current mirror copies the current exactly however it is in subthreshold region.
I am doubtful regarding this whether current mirror perform its duty exactly whether...
I have designed 4 stage NGCC opamp and provide the body bias for all mos in my design ( + Vdd for body of PMOS , Vss for body of NMOS) but it is a coincidence that source and body remain at same voltage for all MOS except Driver PMOS of first differential pair in which I have shorted the body...
Hi, Anhnha;
You can design in any way but you have to take two points in consideration ( for low power small sized MOS );
(1) Vsg > -Vtp
(2) Vsd > - Vdsat
However I think #2 is more convenient as you know ICMR thus calculate in terms of Vg1.
I am explaining for the case when MOS length is less...
Hi, Anhnha;
Id is the darin current entering into MOS while there is some leakage in bulk that's why Ids is some how different from Id. you can verify it in CADENCE.
Hi Anhnha,
I think you should follow the upper limit what Tom has suggested, just replace the Vsg3 in terms of Vsd3. Now for maximum gate voltage Vsd must be equal to Vdsat. In this way calculate Vdsat ( minimum Vsd ). In order to force M6 in saturation use output voltage swing specification and...
Hi, mpig09
I didn't get why are you cascading two MOSFETs as long as first section of your current mirror indicates that you are going to design an effective MOS by simply connecting both gate terminals together and source to drain? Is it necessary for your architecture, if not then try for...
Thanx erikl,
I think dB20(VF("/OUT")/VF("/Vcm")) is Common Mode Range not CMRR and I referred Holberg lecture in which CMRR is dB20(VF("/VCM)/VF("/OUT")). CMRR must be as high as possible...Then where is the problem in my result?
Hi,
As I have already mentioned that I have designed 4-stage NGCC opamp in TSMC 180nm process using Cadence and I got all my specification except CMRR. When I have simulated my opamp I have found that CMRR curve increasing with frequency but it should be decrease as frequency increases. I am...
Hi,
I have designed 4-stage Opamp in TSMC 180 nm process. Can anybody tell me how can I simulate for Total Harmonic Distortion (THD) of opamp in Cadence.
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