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Hi permute,
thank you for your reply.
1) As the matter of fact, { token can be used without backslash, but } indeed cannot. As TML was designed to be language-neutral, some kind of escape sequences is unavoidable. Maybe an approach similar to Lua long brackets can help? I.e. modify the parser...
Hello,
I have developed a set of open-source applications that can be used to create configurable Verilog/VHDL IP cores with graphical confuguration interfaces. It includes a preprocessor that can recognize control tags inserted in the Verilog/VHDL (or other) source code. Control tags can be...
Re: difference between servo motor and 3-phase synchronous m
Thank you sunderwood, I was just thinking the same thing, but I needed someone to confirm it.
Servo motor question
I have very little experience with motors yet, so the question may seem stupid, but...
what is the difference between a servo motor and an ordinary 3-phase synchronous motor? I mean, can I control the latter using an appropriate frequency transformer and encoder as if were...
Is the input signal changed simultaneously with the clock signal in your testbench?
Synchronizing registers are useful when running design in hardware, but during simulation such thing won't help you. So maybe you shouldn't bother yourself with this problem.
Re: vhdl_quenstion
This is a parameter which can alter entity contents at the time of synthesis.
Consider this small code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity csa is
generic (
N: integer:=32
);
port(
A : in STD_LOGIC_VECTOR(N-1 downto 0);
B : in STD_LOGIC_VECTOR(N-1...
Re: needed vhdl code
Do you really mean a dynamic RAM (implemented as a set of capacitors)? If so, I doubt that there can be any possible VHDL description of it.
xilinx xst 2371
In FPGA you should use flip-flops instead of latches, i.e. use posedge or negedge in every synchronous process. Using latches in FPGA design can be considered bad design practice.
how to calculate dc component
Why not calculate mean() of all 1024 samples and then subtract this value from every sample?
(For real systems, some IIR of FIR integrator can be used instead of mean() )
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