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spi vhdl code
Look at www.Xilinx.com they have a SPI reference design for their CPLDs in VHDL:
https://www.xilinx.com/products/silicon_solutions/cplds/coolrunner_series/coolrunner_ii_cplds/resources/coolrunner_reference_designs.htm
pat mpeg
Hi guys,
at the moment I'm building a transport stream filter for DVB-S. When I filter one program out of the stream my0 MPEG-player says that I is not a valid MPEG2 stream because in the PAT are still several programs announced. So I have to modify the PAT and that is where have my...
okay, I think now I understand it.
U can find a short tutorial here:
**broken link removed**
Maybe u can also perform a P&R simulation for the first test.
For a complete test of your FIFOs in HW I would use the UART.
More constraining infomation:
**broken link removed**
Did u infer your FIFO or did u use a VHDL Instantiation Template?
If u use the second u can specify the initial content if the memory:
**broken link removed**
Also useful:
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and
https://www.xilinx.com/bvdocs/appnotes/xapp463.pdf
Hi,
goto to the Xilinx hp:
https://www.xilinx.com/products/spartan3/s3boards.htm
The user guide for the Xilinx Starter Kit contains the complete schematic of the board. The layout can be downloaded as Gerber files.
hi,
U don't say what language u are using. My example is in VHDL. I hope it helps u.
flashIO<=flash_data when write_en='1' else (others=>'z');
flashIO is an input/output dataport to the flash. When the signal write_en='1' the flash_data appears at the output. during write_en='0' flash_IO is...
3.3V, 2.5V and 1.8V
Take a look at the schematics from the Spartan 3 Starter Kit from Xilinx:
https://www.xilinx.com/products/spartan3/boards/s3_board_sch.pdf
CPLD pin problem
LED0 is a std_logic type.
I always use <='0' for std_logic and never had a problem with it.
Is your code for verilog? in my VHDL it doesn't work.
CPLD pin problem
okay, problem is solved.
In the Webpack the option "Create Programmable GND Pins on Unused I/O" was enabled. After disabling everything works fine.
regards
revolt
Hi,
I designed a little CPLD board (xc9536) and now I want to check if everything is fine. So I started to try to toggle pins. That were the trouble began. I use Xilinx Webpack 7.1i / VHDL and want to assign the pins Vccio or Gnd, like this
LED0<='0';
LED1<='1';
But the both pins have a high...
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