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Hi nav_vlsi,
Actually I know that but wat I want to do is estimate approx the interconnect length even before p&r..
Jus by the hierarchy of the design or by the area occupied each module within the top module can we come with a rough idea of the interconnect length is my Q?
regards.
Hi,
I want to know whether its possible to estimate interconnect lengths and their corresponding RC values with just the final netlist(after synthesis) before place and route??
I know it would be approx but is it possible??
Any tools starting from Asic tools to tools in spice ? any way to do...
Hi,
I want to know whether its possible to estimate interconnect lengths and their corresponding RC values with just the final netlist(after synthesis) before place and route??
I know it would be approx but is it possible??
Any tools starting from Asic tools to tools in spice ? any way to do...
Hi,
I dont know abt that but am asking somethin different.
I wanna know whethet jus with a spice model in hand I can compute area of a mos or logic gate.?????
regards
Re: Dependence of propogation delay of a gate on the feature
Hi ,
so u come to say that the delay decrease with decreaing featurewsize.. very true until 135 micro beyond that am not sure? I personally the thinking this dec in deal will not be uniform beyond this??
regards
I want to know what will be the factors which influence the propogation
delay through a gate?
For current lib which is available we can see it from .lib the RC
value..
My question is to know the various factors influencing the delay with
decresing feature size...??????
Regards
in specman instantiation is done by .
Hi,
Am an amateur in Specman tool.. I have a 4bit adder designed using four full adders instantiated within that..
Now I have problem verifying that kind of a block with instantiations within..
Please clarify this and also any sample codes for specman or...
Re: Future???? Nano???
Hi,
No.. am asking about the nano science in general.. as device dimensions are shrinking.. our voltage levels go down.. and many digital charcateristics are becoming analog..
And some more effects like these..
regards
Hi,
how does the reflection of RF waves inside the digital IC damage it..
I know it has detrimental effects but where is the catch.. which parameters are directly and indirectly affected.
Regards
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