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Recent content by renoz

  1. R

    reversible carry select adder

    hi i am doing project in reversible logic please anyone send design of reversible carry select adder and please tell me about how to reduce the number of pins in any circuit using reversible gate over the irreversible logic gate thanks advance
  2. R

    plz anyone correct this coding

    hi anyone correct this below verilog coding,it is 4 bit carrt select adder which contains 3 module ripple carry adder binary excess one conveter mux(6:3) i had error in last part which calling the modules module fulladder(a, b, c_in, sum, c_out); input a; input b; input c_in; output sum...
  3. R

    6:3,8:4,10:5 mux verilogcode

    hi how can write the verilog code for 6:3,8:4,10:5 mux?
  4. R

    reversible quantum architecture

    hi can u send details about understanding quantum architecture of reversible logic gates? thanks advance
  5. R

    reversible gate and irreversible gate

    hi can any one help me about reversible gate, difference between reversible & irreversible gate thx in advance
  6. R

    glitches & hazards

    hi what is the difference between glitches & hazards? please give clear explanation. thx
  7. R

    how memory chip can store the data

    hi how to make memory chip what are the steps to built it? what are the basics,how it can store the data ?
  8. R

    LUT is configured by memory

    hi how to LUT is configured by memory in FPGA? please give detail thanks advance
  9. R

    detail about LUT(look up table)

    hi wt is mean by LUT? send LUT structure, please give detail about this. thanks advance
  10. R

    design flow of ASIC & FPGA

    hi what is the difference between design flow of ASIC & FPGA why these are differ? thanks advance
  11. R

    PLDs & ASIC ,PLDs & FPGA

    hi what is the difference between PLDs & ASIC ,PLDs & FPGA please give detail thanks advance
  12. R

    difference between ASIC & FPGA

    hi what is the difference between ASIC & FPGA please give detail thanks advance
  13. R

    basic cell of each ASIC family

    sorry sir i think you didnt get my question, i asked about building block of each ASIC family(xilinx,actel,altera)
  14. R

    FPGA act as a memory?

    hi how do FPGA act as a memory? please give the clear explanation
  15. R

    cmos… NAND OR NOR & nmos nand or nor

    hello, What technology do we use in cmos… NAND OR NOR? WHY? ·What technology do we use in nmos nand or nor? Why?
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