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Recent content by reddvoid

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    Plotting delay vs. load capacitance in Hspice

    Hi , I am new to hspice I want to plot delay vs. load capacitance I am doing .TRAN 1p 100ns sweep Cload 0f 10f 0.2f $linear sweep this is and .MEASURE TRAN delay TRIG v(A) VAL='HSUP/2' FALL=2 +TARG v(X) VAL='HSUP/2' RISE=2 this just prints the rise delay for different load point sweep Is...
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    Capacitance effect due to more vias and metal straps.

    Updated question
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    Characterisation of standard cell libraries using cadence tool

    for Question 2. you will need hspice model files (or whichever simulator you are using), RCextracted netlist views ...That should do I guess
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    Capacitance effect due to more vias and metal straps.

    L1 output pin  uses M1 for output pin + 2M0 vias to M0 straps L2 output pin  uses M2 for output pin + 6 M1Vias to 6 M1 straps + 12 M0 vias to M0 straps  lower cap than L1 L1 input pin  uses M0 layer L2 input pinuses M1 layer 1 M0 via to M0  lower cap than L1 I have these two...
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    Facing issue of long runtime to find a legal location for cell , in clock opt stage

    Searching legal location of lib cell "BUFFD1BWP240H11P57PDLVT" from (90.00300 227.28000), 4513629 attempts failed, current search location (0.57000 21.60000), current displacement 224.28224 um (934.50934 rows height) Warning: Could not find legal location for cell instance...
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    RedHawk PowerGrid analysis. what are key parameters

    Hi, I am doing Power grid analysis using Redhawk on floorplan db from icc2. (standard cells are not placed yet) .. I am giving .def .lef and custom ploc file as inputs via gsr file , do I need spef file as input here. and what are the main indices/parameters I need to check to see if the grid is...
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    Energy consumed by a digital circuit

    I have a digital circuit , to find the energy consumed by the circuit, I am monitoring the current drawn from the supply and integrating it to get the charge pumped into the circuit ... and the total charge*V supposed to give me total energy consumed by the circuit. But I am getting a small...
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    Peak long and peak short currents

    a standard cell circuit like level sifter, nands, adders etc ansys totem for reliability validation Reliability analysis, Electromigration, self heating, S factor, stuff like that
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    Peak long and peak short currents

    Hi, Can somebody explain what are these parameters physically in a circuit. PKS = Ipeak_short/Ipeak_short_limit , where duration for Ipeak_short is 125ps PKL = Ipeak_long/Ipeak_long_limit , where duration for Ipeak_long is 100ns, or total simulation time (if simulation time is less than 100ns...
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    Hspice not able to output tr0 files properly ? can't see the waveform

    Hi, Thanks for reply I tried .OPTION POST = 1 and .PROBE(*) but its still the same and I don't have waveviewer *st0 file contents* ****** HSPICE -- L-2016.06-2 linux64 (Jul 26 2016) ****** Input File: d04clgpws11wqub0.hsp lic: lic: FLEXlm: v11.2.1 lic: USER: rbm...
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    Hspice not able to output tr0 files properly ? can't see the waveform

    Hi, I have a hspice code I am trying to simulate *** PARAMETER INITIALIZATIONS *** .PARAM LOAD_GTDOUT = 1e-9 .PARAM LOAD_ATOUT = 10f .PARAM LOAD_BTOUT = 10f .PARAM TSTEP = 1E-012 .PARAM PFREQ = 100M .PARAM PPERIOD = '1/PFREQ' .PARAM SLOPE_TIN =8.3n .PARAM PWIDTH =...
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    Logical equivalence between verilog and .lib

    Hi, I was checking logical equivalence between verilog and .lib using cadence conformal I have verilog ports module abcd ( clk, d, o, sleep); input clk, d, sleep; `ifndef INTCNOPWR inout vcc, vcc_in, vssx; `endif output o; `ifdef INTCNOPWR wire vcc, vcc_in,vssx; 'endif but...
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    RTL SAIF and GATE LEVEL SAIF file difference

    Hi, Whats the difference between RTL SAIF file and gate level saif file. I know they are generated from the RTL simulation and gateleven simulation respectively. But Whatever the simulation be, when this switching activity is used in other tools say primetime px for power analysis , doesnt...
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    Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Okay, we can make a design which can consume wide range of CT power It depends on all these factors but typical IC blocks have on an average certain % of combinational cells and certain % of registers and hard macros, can't we assume in general in designes used in industry CT ll consume almost...
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    Average Power consumed by combinational logic in IC : after pnr ; ptpx

    Hi, Thanks for the reply. I am new to PnR please bear with me , Can you give number of standard cells and macro numbers in your design...What would be the % of power consumed by CT for the design with like 300,000 standard cells and around 100 macros. I saw in few designs the CT power was...
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