Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I'm working on the implementation of reed Solomon Encoder in VHDL. Can
you tell me how this block works?
The encoder is based on Galois field arithmetic where the 4 LUT blocks
are multiplied with 12,1,3,15.
We are giving input as 1 to 15(4 bit binary) to the multiplexer. The
control line is...
In the above block Diagram, we are using Galois arithmetic to form an
encoder. here the field generator polynomial(p(x)) and code generator
polynomial(g(x))are taken as follows,
We have used p(x)= x4+x+1
and
g(x)=(x+1)(x+2)(x+4)(x+8)
= x^4+15x^3+3x^2+x+12
The message polynomial is taken as:
M(x)...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
