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Re: Which is the best tool for layout and simulation at home
Hi,
I have been using Electric for quite a long time. It is currently supported by Sun.
For simulations LTSpice and ngspice.
I found three of above are good enough for home usage.
Regards,
Raviprasad K
Re: comparator hysteresis
Hi,
If you can make the comparator sluggish by reducing bias current, it can solve the problem. Basically it is slowing down the comparator output.
In case you need very fast response from the comparator, then adding hysteresis can solve the problem.
Re: Longer channel MOSFET from 2 or more shorter channel MOS
Hi,
In such cases, source degeneration really helps. This reduces the Vt mismatch effect. Larger the degeneration resistor, lesser the effect of Vt mismatch. However, "Larger resistor" is compromise between area and performance...
Hi,
If you are looking for perfectly balanced rise/fall time (Tr/Tf), then pmos to nmos ratio should be equal to kn/kp.
If the inverter is required for very low frequency operation, I do not think you really need to match Tr/Tf, the reason being, period is very large compared to Tr/Tf. Then...
Hi,
This can be explained with an inverter.
If you consider PMOS, it is always sourcing the current and NMOS is always sinking the current. Thus, these are uni directional current.
If you look at the output terminal Y, current flows towards the load when PMOS is ON and out of the load when NMOS...
Re: UGB Problem
Apply Vin+=dc 0.25 ac 1 and Vin-=dc 0.25 ac 0 and then measure gain. Repeat the same for 0.75V.
Important spec to be considered are output load to be driven, slew rate.
Hi,
When I referred to 'normal plot' it is magnitude plot.
Plot the phase noise in magnitude instead of dB. This saves you one step!
Say w1 and w2 are the magnitude plots of two blocks.
Now effective noise w3= sqrt((w1*w1+w2*w2)/2)
Convert w3 to dB plot = 20log10(w3)
You have the effective...
Re: UGB Problem
Oops! It is 0.9mV.
As voltage increases offset should increase. It is Vo/gain. Bias margins looks good enough.
What is the input voltage with which you have checked the gain? Did you check the gain with 250mV input and 750mV input? Are they above 800 in either case?
Re: UGB Problem
Hi,
Gain of 800 means, a systematic offset of 750m/800=0.9V at 750mV input. Thus, you have to increase the gain to make offset below 0.5V.
What is the value of vb1, vb2, vb4? What is Vt of M4 and M8?
Hi,
If you can run the complete PLL in closed loop mode, you can directly plot the phase noise of output clock. But it is difficult to run the simulation for the duration of lock.
If the simulation is done separately for different modules, below is what you can do:
It is random noise. Thus...
Re: cell origin
Hi,
Cell origin is the reference point in layout with which position of devices are measured/displayed. If you place the origin of the cell at the left-bottom of the layout, it means entire drawing is in 1st quadrant of layout window. In this case x,y position of any...
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