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Recent content by ramesh441

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    How the diffusion Sharing transistor folding is done in EDA tools

    Hi, Can I know how the diffusion Sharing transistor folding is done in EDA tools? I want to know the background process of how EDA tools are working in folding a transistor. Thanks in advance, regards, RamesH
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    What is Lsim Power Analyst in Mentor Graphics?

    Where is Lsim Power Analyst & VXL Co-Lsim in Mentor Graphics? I had searched in Mentor site but couldn't find it. Does these tools gort integrated in any other simulator? Thanks in advance, RamesH
  3. R

    Help me on integration of viruoso & eldo

    Thanks for the response. With the help of artsit link we can integrate eldo to casdence
  4. R

    What is difference between Questasim & Modelsim?

    Can I know what is the differnce between Questa sim & modelsim? Thanks in advance, RamesH
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    What is library for Digital Flow in Mentor tools ?

    Dear Friends, I want to synthesize my verilog code in Leanardo Spectrum. Can I know what is the library that supports it other than ADK. for a full Custom flow TDK supports other than ADK Is there any such thing in Semi Custom Flow? Thanking you, RamesH
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    What is SUBSTRATE PLUGGING?

    Thank you Somuch for the reply
  7. R

    What is SUBSTRATE PLUGGING?

    Thanks for the reply, Can I know how could it be done on tool. I am working on Virtuoso environment. Is there any tutorial explaining that. Thanking you, RamesH
  8. R

    What is SUBSTRATE PLUGGING?

    Hi Every one, Can I know what is SUBSTRATE PLUGGING in Analog Layout Design?
  9. R

    Help me on getting 100nm library file

    I want to simulate a hspice code in 100nm and 70nm technologies. Can I know where I could get library file. I didn't find it in MOSIS
  10. R

    WHat is difference between Port and ideal source?

    Can I know what is difference between port and ideal source in analog library of Cadence Virtuoso environment?? Thanking you , RamesH
  11. R

    What is difference between port and ideal source?

    Can I know what is difference between port and ideal source in analog library of Cadence Virtuoso environment?? Thanking you , RamesH
  12. R

    How to extract a capacitor/Resistor?

    I made a layout for a capacitor and resistor on Virtuoso XL There is no schematic for it. I want extract those and the value of it. I am using UMC 180nm lib and its does not provide any diva rules. UMC has ASSURA and Calibre rule sets. WHen I want to simply extract these it is asking for LVS...
  13. R

    Help me on SOC encounter - Saying SOCSYC-*****

    Help me on SOC encounter I did my coding in verilog and synthesized with DC (synopsys). I am using synopsys 90nm (generic) downloaded from synopsys site I want to get layout for it. When I am trying to use Encounter it is giving an error. Saying SOCSYC-***** Can anyone say what I have...
  14. R

    Help me on SOC encounter

    I did my coding in verilog and synthesized with DC (synopsys). My library is synopsys 90nm (generic) I want to generate layout for it. When I am trying to use Encounter it is giving an error. Saying SOCSYC-***** Can anyone say what I have to do ot o resolve it. Thanking you, RamesH
  15. R

    Help me on Sentaurus installation

    I have found out solution for this. Our graphics card was not properly installed. We sorted it out.
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