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Re: regarding CMOS
If Pmos is connected down and Nmos on top ,
For input logic 0:
Pmos ON and Nmos OFF => output is grounded or logic zero (it will not be zero but Vtp)
For input logic 1:
Pmos OFF and Nmos ON => output is connected to VDD or logic one (it will not be ONE but VDD-Vtp)
Re: Unconnected Ports
In Cmos inputs should not be left unconnected.
Output if left unconnected will give rise to crosstalk and short circuit may occur and voltage drop will be high in that net.
Internsic delay is the delay internal to the gate. Input pin of the cell to output in of the cell.
Delay contributed due to internal capacitance of the transistors.
Delay when no external load is connected.
Fanout Delay is due to the fanout load.
its function of i/p transition time of cell...
Re: SILICON nd GERMANIUM
Semi conductor materials are used as building blocks of ICS.
Comming to why silicon.....
silicon has a native oxide i.e (sio2) which acts as insulator between the active regions and differnt metal layers.
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