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Recent content by rakeshrupan

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    Need of Franaszek and Widmer 8b 10b encode decode paper

    widmer franaszek Hi all, Any one have a Franaszek and Widmer 8b/10b source code as well as IBM paper. Please Help i need a IBM paper and Source code. Thanks in advance, Rakeshrupan.
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    What is the maximum data transfer in PCI express?

    Re: PCI express Hi Could any one send me the PCIexpress generation 2.0 Mindshare book. This is very helpful for to me.. Please inform anything about PCIexpress Mindshare Genration 2[PCIe development]. Thanks in Advance, Rakeshrupan.
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    Doubt in PCIe Lane detection sequences

    HI all, I had a doubt in the PCIe Lane detection sequences. If i configured the number of lanes in ROOT complex is 4[ie 4 lanes supported in Motherboard]. When we connected our Endpoint device[it is supports only one lane - 1 lanes] in the ROOT complex Slot means How the Lanes are detected b/w...
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    USB 3.0 and related to Extensible Host controller interface.

    Hi, I want to know How the eXtensible Host controller interface is communication with USB device and Software[Application driver]. IF any one know abt this means Please share your Ideas. I had a doubt regarding Interface and Initialization technique's in the eXtensible Host controller...
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    Need of prime cell dma & synopsys dma related pdf..

    HI everybody, I need a prime cell dma and Synopsys dma related pdf. If any one have it means please send me. This is really help me. Thanks in advance, Rakeshrupan.
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    Need a help for Synopsys VCS compile and Simulate....

    HI HolySaint, Can u give me a Userguide for the Synopsys tool. Really help me for that..... Thanks, Rakeshrupan.
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    Need a help for Synopsys VCS compile and Simulate....

    HI zjushmily/viju, Thanks U very much, Are u have any script for the compilation and loading in Synopsys vcs?. Give me an example. Thanks in advance, Rakesh
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    Need a help for Synopsys VCS compile and Simulate....

    HI All, Could you tell me about how we can simulate my design in Synopsys VCS[Linux Machine]. Give me step for compile and Simulation. This very helpful to me. Thanks, Rakeshrupan.
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    UVC - in CADANCE - Sharing ideas.....

    cadance ideas Hi All, Could please any one tell me about. What is the purpose of the UVC[Universal verification component] developed in CADANCE. How we handle this UVC in our test environment. Any idea about this please share your ideas. If u have any pdf related to this UVC please share to my...
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    Need a clarfication for formatting the Memory card..

    Hi Can any one tell me for the how i can do card formatting in memory card?. Also i want to know the What is the need for FAT in storage devices?. Thanks, Rakeshrupan.
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    codecoverage in modelsim

    HI, Can any one tell me for how we do a codecoverage in modelsim. Thanks, Rakesh
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    Codecoverage - Condition coverage hit cnt prb- modelsim 6.2d

    HI, After merge the report files are updated newly with new count of hits. Hit count not added with previous one. Hit count is updated with current test alone. The conditon coverage rows are changed to new values and the older values are delted and say it is an uncovered one. FOr example ...
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    Codecoverage_error_modelsim 6.2d..

    vcover-6820 HI, Can any one tell me for why the below error occurs in modelsim 6.2d while codecoverage running and enabled. # ** Error: (vcover-6820) Source code mismatch merging ucdb file coverage_report4.ucdb into merge basis E:/CF_xd_ctrl_aug19th/sim/coverage_report_4.ucdb, skipping merge...
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    Need HDL Chip Design book by Douglas Smith

    HI Any one have "HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICS and FPGAs using VHDL and Verilog - By Douglas Smith" book. Please share me. Thanks, Rakeshrupan.
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    Regarding Arbiter logics in DIgital System

    Thanks, Rakeshrupan Added after 10 minutes: Are u have any verilog coding for this ? Please share that. Thanks, Rakeshrupan.
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