Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by raj1234

  1. R

    Current and voltage matching of transistors

    Hey Thanks, Why we use BJT's in 1:4, 1:8 or 24:1 fassion in Band gaps???
  2. R

    How antenna diode works (Antenna effect)

    Hi I have couple of qustions. 1. How antenna diode will work. 2. How charges discharge through DIODE (charges may be +ve or -ve).
  3. R

    Current and voltage matching of transistors

    Yes, I mean balancing current or maintaing constant voltage in the transistors. How to achive this in layout because in some schematic they specify current to be matched or voltage to be matched. I need to know rules to follow ( Ex: like for common centroid distributed, compact,same...
  4. R

    Current matching and voltage matching

    wat is current matching and voltage matching of FET's
  5. R

    Current and voltage matching of transistors

    What is current matching and Voltage matching, Where its used in Analog layout.
  6. R

    About the Calibre LVS

    lvs options allow Hi Dude, I got struck in LVS while running LVS, segment resistor are not recognize as a single resistor and also in LVS Setup option its showing below message LVS REDUCE SERIES MOS NO LVS REDUCE PARALLEL MOS YES LVS REDUCE SEMI SERIES...

Part and Inventory Search

Back
Top