Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Yes it may dominate the total power consumption, because a 4-bit flash ADC has
around 15 comparators. Furthermore the comparators may need precise design
and matching requirements, because mismatch in them can distort the linearity
of the overall implementation. Or you need to use dithering...
If you wish to generate negative voltages, the good strategy is to use
some sort of a charge pump configuration which charges a capacitor
to 5V, and reverses the capacitor terminals. I am not sure whether
you can generate a perfect -5V from 5V, but surely you will get a
negative voltage...
Re: low power opamp
I suppose two stage opamp architecture is a very good cjoice for your specifications,
a differential stage as the first one, followed by a common-source second stage.......
Analog Integrated Circuit Design by Behzad Razavi very well explains the fundamentals of
differential signal processing, and its advantages over single ended signals......
cut off saturation points
VGS is rather a correct measure because, the gate voltage relative to the source voltage
is what decides the inversion of the channel region, and not the absolute volatge of the
gate itself.....
how a voltage detector works
In general for anywhere a system has to be activated based on a threshold voltage,
a comparator with a hysteresis is used, where the hysteresis ensures that after
the system gets activated, its de-activation wont be triggered due to noise or
by chance, unless the...
Re: about CMRR of an op-amp
Read Design of Analog Integrated Circuits by
Paul R Gray and Rober Mayor.
Analog IC Design by Allan and Holberg also
helps.
A high input impedance makes your opamp take
only the input voltage from its source and not any
current. (Imagine your input source as an ideal source
in series with a resistance which is the internal resistance
of the source; your opamp input impedance adds to this
resistance and causes a...
Re: sigma-delta ADC
Subject your ADC output to an FFT to check
its frequency content and compare it with your input.
Most of the ADC tests use this method.
Re: hspice runtime
When your simulation frequency is 400 KHz, keep
the time step as 1 ns, rather than 0.1 ns. Because
higher time step will result in quicker simulation.
If you simulate your circuit at 400 KHz with 1 ns
step, may for a transient simulation of 25 us, your
simulator takes 6...
Usually high pass circuits which have a series
capacitor will act as DC blockers. For example,
all discrete transistor amplifiers which use BJTs will
usually have a capacitor in series with the input signal before
the amplifier. This capacitor will block the DC component
in your input signal...
Perform transient simulation of your USB serdes,
over a sufficient time to accumulate the data transmission
and reception over many bits.
In Hspice, depending on the wavefrom viewer tool you use, you
should be able to obtain an eye-diagram of your result
using the built-in function in the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
