Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi everyone, thank you for reading my post.
I'm doing a project in SystemVerilog and came across this problem.
In the above figure, I want to simulate a signal that has 2 unstable edges (effect of noise in real-time environment). But I have no idea how to make the 2 edges of data unstable. I...
when I use your condition for the design. The almost_empty signal asserts the same time as empty signal. It does not assert like the above picture. This is mi updated code. please correct me.
module rprt_flag
#(parameter ADDRSIZE = 4)
(
output logic rempty,
output logic...
sorry for the late response. I have try and I thank I am half way there. Can you still help.
The problem is that when the read pointer = 14, 15 then the write pointer = ? for the almost_rempty to assert
This is my try, correct me if I'm wrong: (read pointer - write pointer < 2) && (write...
My question is how to design the signal "done" that asserts 1 clk cycle like the above picture. This is where I am stuck. But thank you very much for your reply.
Hi all, in my system verilog project. I am stuck because of a signal below
In this design, done_en is a flag that keeps tract of the generation of 2 bit data_fail. When the generation complete, the done signal asserts for 1 clk cycle to indicate data generation is finished. But I cannot find any...
Hi all, I'm doing a systemverilog project in designing an asynchronous FIFO.
My design is fine until I have to customize the read pointer for almost_empty reneration.
Here is my code :
module rprt_flag
#(parameter ADDRSIZE = 4)
(
output logic rempty,
output logic...
Hi all, thank you for reading my post. I need to design a comparator, because of FIFO problem I have to use the almost_rempty signal to read the data from 1 block (gen block) and signal ren to read data from FIFO block. In the picture below, you can see that when reading the expected_data from...
Hi all, thank for reading my thread.
I have a project that requires a comparator to compare the original data from pattern generation block (TX data) with the data after processed (RX data).
The comparator should assert FLAG as follow:
0b00, 0b11: Prohibited. End of program & assert error &...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
