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Recent content by pumperthruster

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    [Moved] CPLDs and FPGAs contain embedded memory

    I am designing a new circuit that samples an input signal from 1Mhz to 6Mhz(0-1 volt sinusiod). I will use a fast 12bit ADC to capture this signal at 20Mhz. The ADC has a parallel output. I am deciding whether to use either an FPGA or CPLD to grab one single data chunk from the ADC(its a one...
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    fast ADC and fifo or DSP

    I like your ideas. I've being looking at various stuff from Linear and Analog but their demo kits are way overkill,and expensive for my project. The pic32 has a parallel port, DMA module and can run up to 80Mhz. I can get the pic to drive a clk signal for the ADC at lets say 20Mh. The ADC then...
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    fast ADC and fifo or DSP

    Hi Keith, Thanks for your response. I normally use microchips in my projects(I have always used the internal clk however). If I used an External clock to bump up the speed to lets say 100Mhz, this still would not be fast enough. This is because I need to divide this frequency by 10 for a 10 bit...
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    fast ADC and fifo or DSP

    Hello all, I want to sample a signal (DC-6Mhz) and store some 500-1000 samples somewhere for later processing. I don't need to process the samples immediately. I can wait milli seconds for the processing and I only intend to process once every 30 seconds. Cost is a major factor. So far I have...
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    pic assembly macro code that adds a delay

    After spending a whole day on this simple macro for the pic 12f509, I've finally come to edaboard for help. attached is the code. I want a macro that adds a delay. The delay depends on the value sent to the macro. attached is my code.

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