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Recent content by prithivikumars

  1. P

    Regarding output delay /set_output_delay/.

    Regarding output delay. set_output_delay -clock CLK -rise -max -add_delay -0.920 [get_ports]. In the above command output delay is -ve. why it soo.
  2. P

    crosstalk reduction using buffer insertion..

    Hi, iwpia50s is correct. All of you know that the victim is the weaker net then your aggressor. So if you insert the buffer in the victim net your victim net will become little stronger, then you know..... Prithivi.
  3. P

    How to do partition with only netlist?

    Re: regarding partition Hi, I wants the partition using PD tool.
  4. P

    How to do partition with only netlist?

    hi all, If I have only netlist, how to do partition?
  5. P

    Violations on clock nets after doing preCTS in Wncounter

    Re: PRECTS in encounter Max fanout and Maxcap DRV violations are checked irrespective of your clock propagation.
  6. P

    More -ve slack in in-reg path

    Hi, I am getting violation in Pre-CTS stage. Prithivi.
  7. P

    More -ve slack in in-reg path

    Hi, I am having violations in 3000 paths. How to do individually for all the paths? Prithivi.
  8. P

    Which metal layer is preferred for clock routing?

    Re: Clock Routing Hi, If we route in 7th metal layer we will be having more capacitive effect. It will give more delay right. Correct me if I am wrong. Prithivi.
  9. P

    Which metal layer is preferred for clock routing?

    Hi, In 7 metal layer process which metal layer is preferred for clock routing? What is reason? Prithivi.
  10. P

    More -ve slack in in-reg path

    Hi, I am having more -ve slack in i/p-reg path. Is there is any command to optimize only i/p-reg path in magma. Is there any other way to get +ve slack. Prithivi.
  11. P

    max transition violation in soc enounter

    Hi, Max transition violation is b'caz of more load. To solve that do cloning or insert the high drive strength buffer in that path. Prithivi.
  12. P

    Detailed explanation of the SpareCells

    Re: SpareCells Hi, Spare cells we are adding as an Extra cells for future use. Spare cells will be having some logics with them like logic gates and flops. The clock nets also routed to the spare cells and CTS also done. At the end of your design process if the design engineer add some...
  13. P

    Need the library compiler manual from Synopsys

    hi, can anybody upload the library compiler manual from synopsys? Prithivi.
  14. P

    BUFFERS VS CLOCK BUFFERS

    hi, The clock buffers are designed with some special property like high drive strength and less delay. Because clock net is the more fanout and longest running net. Even you can use the normal buffers in the clock path. Prithivi.
  15. P

    How the slew can change the SETUP time?

    Hi all, How the slew can change the SETUP time. Prithivi.
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