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H All,
I have a doubt on blocking and non blocking assignments used inside an always block. As I know, the blocking assignments are executed sequentially while the non blocking assignments are executed concurrently.
An always statement is a concurrent statement while the statements inside the...
Hi All,
I am not able to understand the difference b/w wire and reg when it comes to synthesis. What I understand is that, a reg stores a value when an even occurs on signals in its sensitivity list while a wire is continuously assigned.
I have come across a shift register code, a snap shot of...
Hi All,
Can anyone suggest me about the expectations of an interviewer from a candidate having 2yrs of experience in frontend VLSI design. I have exp in VHDL and Verilog.
I want to work in verification. What are the areas in which I have to update my knowlege.
Plz help me.
Rgds
8 bit alu
Here is the code
DONT FORGET TO PRES THE HEPLED ME BUTTON
module alu(CLK,RESET,A,B,Y,OP,C,N,V,Z);
//****************************************************
// 8 bit arithmetic logic unit
//
// parameter:
// CLK.......system clock
// RESET.....System Reset
// A.........A input
//...
best verilog book
Stephen Brown,Zvonko Vranesic Fundamentals of Digital Logic with VHDL Design.-
McGraw-Hill, 2000.
Stephen Brown,Zvonko Vranesic Fundamentals of Digital Logic with Verilog Design.-
McGraw-Hill, 2000.
both are very good books
Re: how to do this
Here is the code
entity count_40 id
port( clk,reset :in std_logic;
op :out std_logic;
);
end count_40;
architecture arch_count_40 of count_40 is
signal count:integer(0 to 41);
begin
process(clk,reset)
begin
if (reset= '0') then
count<= 0;
elsif(clk'event and clk='1')...
Re: Sync or async design?
Firstly I would like to thank you for the reply.
I tried an async D flip flop in ISE. But i didn't get any warnings. I am using ISE 9.1
Can you plz suggest how can I learn Timing analysis in Front end design? I mean any evaluation version tools ?
Sync or async design?
Is synchronous or asynchronous design prefered?
Plz give reasons. Async design is usually infered by a Latch in FPGA design while sync design by a flop.
So, which is the better idea of designing?
Hi All,
I want to get some information regarding where can I buy "Impedance pressure transducer of 5 mm in diameter and 1mm thick". I tried to find in google. But couldn't get any information. Kindly help me. Its urgent.
Thanks
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