Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by prashanthaditya

  1. P

    "protected" keyword support for Design Compiler??

    Hi, Please let me know whether "protected" keyword ( Defined in VHDL-2002) is supported by synthesis tools ( Design Compiler)... Thank you all in advance.
  2. P

    Help me solve a slack issue in a circuit

    Hi, Please advice me in solving the below issue Am using v5fx70 ans ISE 10.1 Thank you for ur time... ------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing...
  3. P

    How to introduce synthesizable gate delay in Gates of xilinx

    i want to implement an AND gate with a delay of 5 units in it. eg : and #(5) a1(out,in1,in2); but the synthesis tool is removing the gate delay how should i implement the same in synthesis way If i check the gate level netlist i see it implemented an LUT how should i take an AND gate which...
  4. P

    Levels of Logic in FPGA...how is it related to frequency

    hi all, what is Levels of logic in FPGA how is it helpful in increasing the frequency of operation of a logic without changing RTL. thanks
  5. P

    what to change RTL to make logic work from 150mhz to 400 mhz

    hi all,we are faced with this issue. we have developed RTL for Actel which works at 167 MHz (required was 150MHz) now the same RTL has to be ported to work at 400 MHz. what are the steps to be followed at RTL level such that we can achieve the frequency. we checked the synthesis but there is no...
  6. P

    Parallel Read and write in AHB-AXI bridge

    ahb axi bridge Hi, I am just confused in AHB to AXi bridge operation i.e How can we achieve parallel read/write operations in AHB to AXI bridge. When two masters are accessing same slave ?? Is it posiible, becoz AXI can support both read/write at a time... Please sugget P
  7. P

    Using AHB split transfer in FSM

    Hi Guys, In AHB,when slave can give spilt response to the master based on its decision. Thats why when you implementing in a FSM (slave interface) , to give split response to master,how will you judge split transfer?? I mean to say on which condition your FSM will give split transfer to...
  8. P

    AHB master and slave interface

    leon3 ahb add slave Hi, Anybody is having any materials regarding AHB master and slave please share with me. Anybody have RTL code of these modules please share. P
  9. P

    AHB-AXI bridge and its various aspects of design

    ahb to axi bridge Hi All, Can anybody tell me about AHB-AXI bridge and its various aspects of design. What will be the exact functinality of this???? RRRR
  10. P

    Information for coding SRAM controller in Verilog for CYPRESS SSRAM chip

    Please provide me any links or information for coding SRAM controller in verilog for CYPRESS SSRAM chip. Thank You.
  11. P

    SDRAM controller, offchip n onchip memory?

    Thank you Ramesh, however it requires an account which i don't have. please upload the file or provide any alternate link if possible. Thank you.
  12. P

    SDRAM controller, offchip n onchip memory?

    Hi all, How the communication takes place between the SDRAM controller, one offchip memory and one on chip memory ? Can controller transfer the data between off chip memory n onchip memory? Thanking You in advance!!!!!
  13. P

    Any body worked on USB 2.0.

    I am designing a SDRAM controller with AXI interface for a USB device. Can any body tell me how the communication takes place between SDRAM controller, Processor and Protocol Engine? I mean for read or write process whether the protocol engine will send signals directly to the controller or it...
  14. P

    AXI interface with SDRAM controller?

    I am designing a SDRAM controller with AXI interface. Right now am using only one bank for read and write upto a burst length of 4. 1. How I should modify my code such that I can have the control on all the four banks. i.e: when one bank is writing or reading the data, I want to activate other...
  15. P

    Querry reg AXI slave interface

    Hi all, I am working on AXI bus protocol. What does the AXI slave interface consists of .. i mean what is the main purpose of that. Pls provide me some info . Thanking you all.
See more

Part and Inventory Search

Back
Top