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ddr3 write leveling
Does any body know how the implementation from the controller side look like regarding write leveling? Does the controller need to generatae any enable signals to control the delay to be added to the DQS signals and if so, how does the controller how much delay it should...
there is no point of blocking and non blocking assignments w.r.t the question asked by digital-newbie.
If he wants to have shift in every clock cycle, input d shoulb be toggling in every clcok cycle. Check the input "d", if u give 4'b1111 as input and at everyu clock edge u will see the o/p...
u r approach is the one which is similar to my implementation...only thing which u need to take care is read and write at the same time with address locations and read and write with same address has to be bypassed.
ddr_ddr2_sdram.zip
I just wanted to look at the way they have implemented the DDR2 controller, if you have the verilog code of DDR2 controller, can you upload them.
I have 4 years of experience in Digital Design and Verification. I am planning to relocate to India. It would be great if some one of you refer me in your respective departments/company. Looking forward to get some guidance.
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