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Thanks Erkil, I assumed that since bonding wires are good thermal conductors - the heat in the bonding wire would be easily conducted out of the chip through the wire and the pins. So that heating effect can be left out of the equations. Also what does
Theta-PA stand for...
The IC I am designing has a power mos inside it. Half the power loss is in the MOSFET and half in the bonding wires to connect the MOSFET. When calculating the junction temperature of the chip based on the package Theta-JA and the ambient temperature, should I ignore the loss on the bonding...
Hi Dick,
Just an update - eventually I decided to connect the ESD cell to GNDA to avoid having to do the ESD analysis the way you explained.
ESD to GNDA for this particular pin means slightly more switching noise but not catastrophically so. Sadly my (tiny) company does not have a strong ESD...
Hi Dick,
Thanks, I understand your point about looking for the most likely path for ESD discharge for the one pin that is connected to GNDP and making sure that path can handle the ESD stresses.
That aside - lets assume GNDP was connected only to the gates of FETs. And I have this one pad...
Sunnysky thanks - that is a interesting idea. I may consider that.
Just wondering also assuming I dont change anything from my original plan - do you have an estimate on how much the yield is lowered due to wafer level ESD failure?
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Thanks AMS but it may be too late in...
I am designing an IC with two separate grounds GNDA and GNDP. The two grounds are not connected to each other on chip. But they will eventually be bonded to the same pin on the package. Also there is no antiparallel diode connection between GNDA and GNDP at the chip level.
My question is...
Hi,
At my company we have an opportunity for a junior level - power management IC design engineer in Singapore. Prefer someone with at least a couple of years analog/ power management IC design experience (at least one full tape out cycle). International candidates are welcome. If you are...
We are looking for an experienced (5+ years) analog / mixed signal IC layout engineer in a publically listed IC design company in Singapore. Tools experience with Tanner L-edit is a plus.
Please send me a private message me if you are interested and I will get back to you if I feel your profile...
I am going through Middlebrook and Voperians work on the extra element theorem. I succeed to prove the extra element theorem with Z open, Z short, gm-->0 (dependent current source), A-->0 (dependent voltage source).
What I can't seem to figure out is how to prove the EET for dependent sources...
Anyone want to take a shot? If you feel the question is missing details - do let me know. I have some implementation ideas but I would like to hear some ideas first to get a discussion going.
I have an incoming variable frequency (1 KHz to 20 KHz) and variable duty cycle pulse. I need to convert the duty cycle into an analog voltage between 0 and 1. I do not have the luxury of RC filtering the pulse using an external capacitor.
What is the simplest way to implement this function on...
Chuckey, your post is not exactly answering the question. Or did I not catch your meaning?
Another question related to electronic tranformers:
1) If there is no halogen lamp connected on the secondary, will the electronic transformer still have oscillations? I have read a few articles saying...
Hi,
I have a question about electronic transformer circuits that are used to drive halogen lamps. The questions are based on the attached document on the subject.
Regarding this document in Figure 1:
1) Is the self oscillating frequency constant? It seems that as the rectified AC input...
Hi,
A well funded hardware start-up in Singapore is in need of a Senior Electronics Design Engineer. I happen to be friends with the HR Manager and I am posting this as a way to help them find a suitable candidate. Anyone who is interested, please PM me.
The job description is as below...
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