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ltran ic
How u define LTRAN & RTRAN in term of TEMP & VDD...
i know LTRAN has n-type MOS fast,p-type MOS slow & on the contrary RTRAN is n-type MOS slow, p-type MOS fast...but im still clueless about fixing the Temperature & supply for my sims...DO anybody have the info about this
Im trying to simulate the open loop ac analyses & closed loop dc gain for the logarithmic amplifier which been attached below. Im not pretty sure about Testbench that i should create. Plz advice. The testbench that i;ve tried is by giving a cap & vsin in series wif a big inductor value at the...
For a normal CMOS amplifier, we can play wif the Cap/Res as the F=1/RC. But im quite unsure on how to increase the Bandwitdh of the Bipolar LOg Amplifier. The cct shown can contribute about 100kHz operation. How to alter this circuitry for it to work at higher frequency?
Could anybody tell, what is the salary range for 2-4years experience IC Design Engineer neither Analog/Digital in Singapore ? What are the other benefits do they offer such like stock option,etc ?
Would like to know the opportunity & current market for an analog designer in S'pore with 2 years of experience. Whoever working in Spore please feel free to drop ur valuable views
Im engaged with one of MNC company in M'sia...looking forward for a career at S'pore in the same field. Having 2 years experience in Analog design such as ADC, PGA,op-amp,PLL,VCO. After some browse through i've found some of companies such Mediatek, Institute of Microelectronics..is there any...
skew lots
I dont have any knowledge on how this skew parts(FF,F,S,SS) been differ from each other. I know that there is some standard split depends on the process technology. But atleast i need to get clear of myself on they ben define first of all..
I'd done some primary browse & got to know...
skew lots
Skew lots(FF,Fast,SS,Slow,)...in term of process terminology how to differentiate this 4 corner process. I've a Nominal part with me, which i need to characterize to distinguish the difference compare to all the 4 corner cases.
But i dont rely get it how they differentiate this, for...
i have this 10-bit pipeline ADC that operates at 6.75Mhz, i wanna test INL & DNL factor for my ADC, i knew it supposed to be done using transient analyses...what type of input i should give, i've differential input in to ADC. ANd how long u need run & how many hours does it takes???
spice simulation dac dnl inl
i have this 10-bit pipeline ADC that operates at 6.75Mhz, i wanna test INL & DNL factor for my ADC, i knew it supposed to be done using transient analyses...what type of input i should give, i've differential input in to ADC. ANd how long u need run & how many hours...
inl dnl fft
im not quite sure abt all this testbed(cct) for testing pipeline ADC performance such INL,DNL,SNDR & FFT using Cadence. Do anyone have some testbench cct for these performance metrics ? i knw it need to be done in transient.. but how about testbed signals ???
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