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Recent content by piyush.kanodiya

  1. P

    DNL ,INL calucation for Flash ADC

    here with, i attach DNL,INL graph for 5bit flash adc, but there is deviation between ideal graph and i obtained...any one help me.. input voltage vin sweep form 0-1.4V ramp rreference voltage vref= 0.7v clk= 500Mhz VLsb=43.75mv
  2. P

    problem with charge redistribution DAC..

    Hello, i m working on successive approximation ADC,. for that ,i have to design DAC ,which one is better,,resitor string,,R2R ladder, or charge scaling..? i choose charge scaling...but in that i have one problem with,,capacitance value.. how we decide capacitance value for any charge scaling...
  3. P

    Need help with 12 bit SAR ADC design

    Re: sar adc gilbert promitzer i m working on Charge redistribution DAC...Do u have any idea on it..please post it.. thnks Piyush
  4. P

    problem with SAR ADC design in Cadence ?

    Hello, i am working on SAR ADC design in cadence schematic composer..i am getting proper ouput from shift register but after shift reg. to SAR register ,not getting proper output...can any one help me? for 5-bit DAC , shift register output is 10000 but therotically,we get out of...
  5. P

    Can any one have idea on SAR Register implementation?

    Hello, Can any one have idea on SAR Register implementation? what is actual circuit design of SAR register? thnks in advance, Piyush
  6. P

    How does SAR register function in SAR ADC?

    Hello, I have a problem with SAR ADC. i don't understand actual working of SAR register and how SAR regisrer design.. for SAR ADC, what we have to apply as a input to shift register. one input is our clock signal and one is either our sampled output of S/H ckt. or our actual analog input...
  7. P

    What is the actual circuit of successive approximation register?

    Hi, can anybody tell me actual circuit of Successive aaproximation register..After Shift register ,data bit stored on SAR register..so which type of register is this...and its output goes to DAC part.. Thnks
  8. P

    prblm with cadence schematic file using verilog code

    How to create schematic file in cadence schematic composer using verilog code?
  9. P

    How to create schematic file in cadence schematic composer?

    hello, How to create schematic file in cadence schematic composer using verilog code as a instance?
  10. P

    How different block S/H,comparator, Shift register, SAR logic implement with Cadence?

    hi, i m just starting the designing of SAR ADC.. any one help with this..how different block S/H,comparator,Shift register,SAR logic implement with Cadence tool.. thnks, piyush
  11. P

    Looking for a circuit diagram of SAR ADC

    any one help with internal circuit diagram of SAR ADC... Added after 1 hours 19 minutes: i m just start with ADC data converter...reading many books but still confuse with internal transistor level circuit of different ADC architecture.. any one suggest me regarding SAR ADC internal...
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