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One Clock Pulse?
If you are generating the ack signal on some request pos edge, it might be something like this ...
input req;
output ack;
reg req_reg;
always @(posedge clk)
begin
req_reg <= req;
end
assign ack = req & ~req_reg;
Hi,
I have a doubt regarding GLS. We are designing a very large complex SOC now we are running GLS but since SOC is very complex, compilation and elaboration are taking 6-7 hours. So, It is very difficult to do the GLS in this case.
Is only STA timing closure is enough here? what you guys say...
Hi,
How is the future of the "E" and "vera"when everyone is moving towards system verilog? As all verilog simulator is going to support system verilog now or in near future so no extra licence is needed as in case of specman or vera? Even system verilog has almost all features of OOPS like...
HDL path is ur DUT hierarchy as for example ~/top/DUT/ARM_1/AXI_IP/
while e path is for test bench which starts from SYS as for example sys.env.monitor for monitor unit under top enviroment which is under sys.
It is basically used for functional coverage. Here you can some valid coverage points of ur design and you can see how many times ur coverage point got hit.
Added after 2 minutes:
For example u have address and data then you can define coverage point for coverage group address and data. All...
Verification plan is written after reading the specs of design i.e what are the features ur design has and how are u going to verify those features.
Verification for different projects will be different assuming they have different functionality or features.
If they have some features same...
Netlist Validation
I think netlist validation you mean formal verfication which can be done by formal tools like LEC, conformal where they can compare netlist and golden RTL if there is any mismatch or not.
Can you elaborate about netlist validation meaning?
Regards,
Basically there is no difference between these two ....... Both are refered to same thing.
Some people might say verification plan as overall SOC verification plan and test plan as tests written for how to verify each feature of SOC/ chip.
But both are for plan created for verification of a...
Hi,
Here 4th will infer a single flop with d->q
2nd and 3rd are equivalent since non blocking can be put in any order and they will infer two register with d->p->q
1st will also infer two flops d->p-> q .
gate sim with -ve delays
You have to take care of many things during gate sims run.
1. If you are using same RTL simulation verification enviroment for gate sims then you have to put some delay while driving the inputs as here setup and hold come in picture.
2. You have to initialize all...
interview questions systemverilog
Yes i completely agree with boardlanguage ...... if you know system verilog then only you can give the answers of most of them.
emacs systemverilog
Hi,
does anyone has *.pl fle for emacs for system verilog support? I am using emacs as editor but my emacs does not have supporting file for system verilog. Where can i find this?
Thanks,
system verilog interview question
I think if you have learnt system verilog .... then most of questions can be answered ......... You can refer to book Verification using System verilog by chris Spear.
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