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Recent content by pigtwo

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    Cadence Allegro(17.4) How to assign an etch arc a net.

    Hello, I'm working on a design in Allegro 17.4 where I need to use circular etch arcs. I've done this plenty in Altium and it's super easy. But in Allegro I can't seem to find a way to assign a net to a circular arch. In Altium you'd have some parameter that can set the net but I don't see that...
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    Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    @barry Yep, that does seem to be my problem. I used two OSERDES2 primitives in parallel each driving one pin of the ODDR but with the image niciki posted that doesn't seem to be possible. The only reason I did this was because I need a 10 to 1 serializer but the OSERDES2 only allows a max of 8...
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    Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    Hello all, I'm working on a simple DVI driver in a Spartan 6 and I'm running into a routing problem. To transmit the TMDS signals I'm trying to create a 10:1 serializer. I'm using two sets of OSERDES primitives each generating a 5:1 serializer then I'm using a ODDR primitive to do the final...
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    18ns Path delay from reg output to output pad - Sanity check

    I think you're right about something in my constraints implying I need a large delay. To be honest I had to create the constraints by converting from UCF to XDC and this is my first time using these constraints in both UCF format and XDC format. So I likely did something wrong. Below is the...
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    18ns Path delay from reg output to output pad - Sanity check

    I believe clicked on the correct locations. That arrow is drawn by Vivado when I click on the path in the first image(the highlighted one). Clicking 'Routing resources' in menu bar(is the way to open routing view?) shows the below: I believe the white line is the actual route taken. I'm...
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    18ns Path delay from reg output to output pad - Sanity check

    Hello all, I'm working a project that I'm trying to migrate from a Spartan 3 to a Artix 7. I'm running a quick test on a dev board to verify there are no major problems before we commit. But I'm running in to a weird problem in timing. I'm seeing really long routing delays(>18ns) for fairly...
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    Define 2 dimensional localparm in Verilog

    You're correct, it appears to be System Verilog syntax. I tried what you suggested by initializing it in a initial block and that worked. And you're right that readmem can do the same thing. Thank you!
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    Define 2 dimensional localparm in Verilog

    Hello all, I'm trying to define a set of coefficients for some DSP inside a FPGA but I'm running into a problem with defining the coefficients. I want a 1000 element array with each element being 18 bits. I'm running the below code: localparam num_taps = 1000; localparam coeff_scale = 16...
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    [Verilog] Task inputs assigned right before task call - Race condition

    Hello all, I have a fairly simple question about tasks with inputs. I've been working on this problem where I assign some values to a register then use those values as the input to a task. I've found that when I call the task the values it takes is the previous value of the input. I created an...
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    [Verilog] Testbench Critique - First attempt at a real test bench with verification.

    Ah ok, that's good to know. Thank you again for the advice. I think I have a much better idea of what I should try to do now. I'm going to have to spend some time familiarizing myself with SV. Then I have another module I need to write for this project so hopefully I can apply some of this...
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    [Verilog] Testbench Critique - First attempt at a real test bench with verification.

    That makes sense. I think the problem here was when I first started I thought the idea was to first build a model of the ADC that would just respond as the ADC would. Then you could run tests against it. But obviously all the tests will be in the model and it becomes very cumbersome. I'm...
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    [Verilog] Testbench Critique - First attempt at a real test bench with verification.

    @ThisIsNotSam That's what I thought I was finding while researching this. Almost everyone seems to reference SV. I started looking into it but I can't seem to find a simulator that can simulate non-synthesizable SV. @TrickyDicky Thank you for the input. I think I understand what you mean...
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    [Verilog] Testbench Critique - First attempt at a real test bench with verification.

    Ok, I was sort of thinking that. It seems the only thing to check here is basic timing and whether data makes it from one end to the other. I'll be using this in a larger design so maybe that one requires different strategies like you mention. As I mentioned I'm not really sure to what...
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    [Verilog] Testbench Critique - First attempt at a real test bench with verification.

    [Verilog] Testbench Critique - First attempt at a real testbench with verification. Hello all, A month or so ago I posted about wanting to get better at making testbenches. Previously I just used basic logic to create the signals and respond accordingly. This was super tedious so I've been...
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    Large voltage spikes during transitions of common emitter circuit

    @FvM Ok, that's what I was starting to think. I simulated clamping to ground and this did remove the negative going spike. I think I understand the basic idea here but I'm a little confused. From your description the problem arises by the high frequencies coupling through the base to the...
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