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How can you model a SRAM at RTL Level?
Also
How to generate sine wav using verilog coding style?
How do you implement the bi-directional ports in Verilog HDL?
Is Verilog (or that matter any HDL) is a concurrent or sequential language?
What is the function of sensitivity list?
Why would a testbench not have pins (port) on it?
When declaring a flip flop, why would not you declare its output value in the port statement?
Why would a testbench not have pins (port) on it?
When declaring a flip flop, why would not you declare its output value in the port statement?
Is Verilog (or that matter any HDL) is a concurrent or sequential language?
What is the function of sensitivity list?
A “tri state “ bus is directly connected to a set of CMOS input buffers. No other wires or components are attached to the bus wires. Upon observation we can find that under certain conditions, this circuit is consuming considerable power. Why it is so? Is circuit correct? If not, how to correct?
Name the fundamental 3 operating consitions that determine (globally) the delay characteristics of CMOS gates. For each how they affect gate delay?
For a single gate, with global gating conditions held constant , what 3 delay coefficients effect total gate delay? Which is the most sensitive to...
What are the two most fundamental inputs (files) to the synthesis tool?
What are two important steps in synthesis? What happens in those steps?
What are the two major output (files) from the synthesis process?
A mealy –type state machine is coded using D-type rising edge flip flops. The reset and clock signals are in the sensitivity list but with one of the next state logic input signals have been left out of the sensitivity list. Explain what happens when the state machine is simulated? Will the...
Delay decreases as u decrease ur th voltage as switching time decreases and abt the mobility it will increase till a certain point as temp increases It has to do with the work function i guess just check.
Re: maximum frequency
In the ckt C2 is skewed after C1 so
according to eqn
tw>=max tpffD1 + max tcombi + tsuD2 - mint of the gates affecting the clock 2
tw>=max tpffD1 + max tcombi + tsuD2 - mintinverters
tw>= 2ns + (1+1+1+2) + 3ns - (1+1)= 8ns
freq=125 Mhz
Re: register question
So for SIPO the output will be available at 8th pulse that means the answer is 800MHz is that right basha ji?
Added after 1 minutes:
sorry 800ns!
Re: max operating frequency
Guy's I m more confused now....
nand_gates why r we not considering the hold time of the first flipflop can u plz xplain?
thanx for ur support guys
Clock Gating
It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.But, a latch implementation is widely used to avoid glitches
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