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On-wafer test or packaged test?
If it is on-wafer test only, you should take all traces on the chip into simulation. These traces should be packed as RF elements.
If it is packaged test, you should also take bondwires, leads into simulation.
1. Active device still has several certain parasitic resistors.
2. The output power of LNA depends on the input power and the gain. So, this concept is not exists.
3. Resistor can be used in LNA design, i.e. bias part, etc. But you had better not use resistor in signal path, especially for...
For single nwell MOS technology, the bulk of NMOS transistors must be connected to substrate. Therefore, its source and bulk have different voltage levels.
corner simulation
A constant current bias is a must. The current value should not sensitive to the variation of process corner, supply voltage and temperatue.
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