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Re: Probe pads Used in IC
Hi,
Probe pads are basically test pads to know voltage or current at that point.
In general for critical points (places), we put test/probe pads.
The layout rules for probe/test pads are in process file (DRC file)
In general the nwell of nwell resistor is not connected to any potential because for that resistor we didn't define any potential, please correct me if i am wrong..
Re: dracula !!!
Hi
r u using dracula with GUI run and command line run.....
inboth ways it is not difficult if u know basics and laso it is similar to calibre.
if u r using GUI, u can easily debug the DRC and LVS errors.
Regards,
Penchal
Hi Sandeep,
In genreal we made holes (slot/slit) for wider metals to avoid break up of metal due to thermal expansion during fabrication (same as railway tracks).
The width and length of hole/slot will decide by FAB process, if the hole width and length is less than recommended values then...
Dear SP,
Analog Layout is not polggon pushing... your thinking is totally wrong...
if u imagine ur layers (layout polygons) with physically, then it is intresting.
Re: power bus width
Width of Power Metal line depending on Electro Migration(EM) and IR Drop.
These EM & IR depend on process and technology. The current density and resistance are different for diferent metal.
Regards
Penchal
interdigitising in layout
Hi,
inter digitization is inter mixing of required matching units, if we use this we can not match in all directions.In common centroid, the center for two require pairs should be same. so it match the two pairs in all directions.
for e.g if we want match two txrs...
Re: Stack Via
Yes, generally (in new technologies) we place one via over other via, for e.g via1 over via2.
what r advantages n disadvantages by placing like that (stacked via).
Re: metal width
Hi,
As our friends said, first we have to check how much current (dc,rms,avg) will carry for 1um metal width. According to current requirement we have to calculate metal width.
Metal width=required current/current carrying for 1um metal width.
Apart from this metal width also...
Hi,
In General for dummy Txr, we tied all terminals together and connected to VDD if it is PMOS or it is connected to VSS if it is NMOS.
i didn't how it is acting as decoupling cap because for any CAP require two terminals but here we are tied all together i,e. it is single terminal, plz clarify me.
Hi All,
why we make always resistor with poly,nwell.......but not with active even though active(P+/N+) having more resistance than poly and well. plz clarify me
Thanks
Penchal
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