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Recent content by pavithra226

  1. P

    physical design fixing violations

    i am working with soc -encounter. while routing the no violations were reported. but when verified with calibre -lvs its showing 4 incomplete nets. when checked for same nets in soc - E those are no connected as required. what would be the reason & how to overcome such violations.
  2. P

    cadence encounter manual/user guide version 10.1

    Can anyone please provide eith Calibre PEX manual for version 2009.2? Any other version is also ok
  3. P

    physical design fixing violations

    How to ovecome the DRC related to Metal & via. How to control the routing layers & vias?
  4. P

    physical design fixing violations

    Why do we get Min-step violations at the sign-off stage? What is its significaence?
  5. P

    physical design fixing violations

    actually this wont help much, If u again check for DRC the violations appear as it is
  6. P

    physical design fixing violations

    after this am getting min area & min step errors how to go about that?
  7. P

    physical design fixing violations

    i want to clear density violation not fanout
  8. P

    physical design fixing violations

    thanx yadav At the sign-off stage how to overcome denity violations? i tried editFixWidewires but it dint help much. Can you please suggest any solution?
  9. P

    physical design fixing violations

    @yadav: am getting these viloations at the sign-off stage affter adding bufers to componsate transViolation. So, does deleting these nets causes deleting any of those buffers added? Also how to fix SI(signal integration) errors?
  10. P

    physical design fixing violations

    how to fix geometry violations such as shorts,wiring & sameNet erorrs?
  11. P

    physical design concept query?

    What is Antenna effect , cross talk, IR drop, Multicut via, multicut metal.mincut via & mincut metal mean?
  12. P

    physical design fixing violations

    What is Antenna effect , cross talk, IR drop, Multicut via, multicut metal.mincut via & mincut metal mean?
  13. P

    physical design fixing violations

    how to fix fanout violations? i already did seOptMode -fixFanoutLoad true fallowed by optDesign -preCTS. so how to fix the violations manually? What is the difference between preCTS, CTS, postCTS & postCTS_hold steps?
  14. P

    physical design fixing violations

    how to fix maximum capacitance violation, max transition violation using cadence encounter
  15. P

    What is CLOCK TREE SYNTHESIS

    what are the diffrence between via & contact

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