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Recent content by pavan.mk

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    Need help in writing a tcl script to find out cells in the clock path

    In this example , Other End Arrival Time 3.278 - Setup 0.470 + Phase Shift 25.000 + CPPR Adjustment 0.000 = Required Time 27.808 - Arrival Time 26.292 = Slack Time 1.516 I see that there are two arrival time values. They both represent the time from the launch registers CLK pin to capature...
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    Need help in writing a tcl script to find out cells in the clock path

    Thanks sam536 :) Do you have any idea about other end arrival time? This I came across when I was analyzing a timing report.
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    Need help in writing a tcl script to find out cells in the clock path

    I am using RTL Compiler.
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    RTL Compiler : Any command to find out cells driven by multiple clocks

    HI ED, Thank you. But how can I differentiate the cells which are having multiple clocks? There should be a mux output which is connected to the clock pin of the sequential element. How can I find this?
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    RTL Compiler : Any command to find out cells driven by multiple clocks

    Hello everyone, Can anyone suggest me how to find out if any sequential elements are getting driven by multiple clocks? Is there any command in RTL Compiler to find out this? Thanks in advance.
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    Need help in writing a tcl script to find out cells in the clock path

    Hello everyone, Can anyone tell me how to find out the cells in the clock path? I am trying to write a tcl script to find out the cells in the clock path. Thanks in advance
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    Regarding setup and hold violaitons

    Ok, thank you sir. Regarding congestion, we say that whenever the required number of tracks is less than the available number of tracks then it leads to congestion. How do we get know the required and available routing tracks?
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    Regarding setup and hold violaitons

    Thank you sir. In the SDC file, we provide set_input_delay and set_output_delay. Why do we use that? And how would we be able to fix those values?
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    Regarding setup and hold violaitons

    Regarding setup and hold violations 1) Can anyone tell me equation wise how we calculate setup and hold slack? (including uncertainity and skew) 2) How do we fix setup and hold violations? 3) Why hold analysis is done after clock tree synthesis? 4) How setup check can be done even before clock...
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    digital design using hardware description languages

    I agree with yadavvlsi. The delay constructs are not synthesizable, in the sense that, those values are required only during simulation where you test your RTL and observe the delay what you gave in the waveform. But once synthesis is done, the actual delay value of the gates and routing delay...
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    Need help regarding LEF and LIB files

    Hello everyone, This post is regarding .lib and lef files. I wanted to know exactly what these files contain. According to my knowledge in LEF we have - Tech LEF, Cell LEF and Macro LEF. I don't know what each of them contain. In a .lib file, we the operating conditions(PVT info), cell...
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    Need guidance for physical design flow(cadence)

    Thank you yadavvlsi.
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    Need guidance for physical design flow(cadence)

    Hello everyone, I am a physical design trainee and I wanted some guidance regarding the physical design flow. How should I start for it? What all I should learn? Please let me know what all I can refer to. If anyone can give me a brief information regarding the flow it would be really helpful...
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