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Re: What to do if post layout timing not matching to synthes
Pre-route and post-route will check differently. synthsis meet doesn't mean meet in post-route. some path only be checked in Post-route, unless you modify some default option when synthsis. ideal clock and CTS are also differently.
because start from DC0412, constant register will be delete. you can
set compile_delete_unloaded_sequential_cells false
or set_dont_touch on the constant_register,
I feel (2), (3) has no prolem.
astro can do with "assign" now.
In fact, the important thing is you need check sdc with PT firstly.
see whether sdc is not reasoniable.
clock gating check
if you use power compiler insert clock-gating, use
propagate_constraints -gate_clock
it can add clock-gating check . otherwise you need add:
set_clock_gating_check -rise -hold 0 [get_cells {..../main_gate}]
formalVerification use lec, formality tools to check the logic.
functional verification use NC or vcs to run your function pattern.
Sometimes formalVerification can pass, but functional verification will fail.
for example, timing, reset problem...
I once design GPU for 4 years. Now I left , becuase NV & ATI is too powerful, we can't catch up with them. Graphic is very complicate, you can learn from DX9 and OPENGL. There are some PPT files you can get from Stanford university web.
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