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From the schematic posted it looks like A, B and C is a current mirror where B is the diode connected device, place this in the centre of the array. Likewise D, E and F look like the cascodes to the ABC mirror, E seems to be the diode connected device here so it should go in the mirror...
Cheers for the input Erikl, I can only think the crystal structure idea is when a device is placed perpendicular to the reference and I have got mixed up.
Many thanks.
So implant shadowing is definately one reason, thats good I have an explanation.
I have also read that the crystaline structure of silicon has an effect. I can understand why this would lead to mismatch between devices that are at right angles to each other, however I don't understand how the...
It seems that you need to match B to A and C and D to E and F. Unless my designer specified that matching was critically important here I would be tempted to layout
*ACBBCA*
*ACBBCA*
*ACBBCA*
*DFEEFD*
*DFEEFD*
*DFEEFD*
* is dummy device
What geometry are you working on (0.35um, 0.13, 65nm)...
I'm looking for a bit of depth to my understanding of matching techniques.
As I understand it to achieve a well matched mirror it is important to match the direction of current flow in the reference device and the mirrored device, i.e. if you have two transistors sinking 1uA drain current...
In the past I used to use a tool that would take a LVS clean layout create a view showing only the metal layers attached to a supply pin. This was very handing to make sure there was not any blocks relying on minimum sized wire for their supply leading to IR drops and electromigration issues.
I...
I understand about the well proximity effect and your understanding of it is the same as mine that matched devices should not be placed close (within 2 or 3 um) to the nwell / substrate boundary.
What I meant was in the picture above the devices A and B in structure 1 were protected from STI...
analog digital ground layer
Depends on the process, however if you have a deep trench option then I would recomend placing a guardring around your digital section tied to digital GND, then drawing a ring of deep trench isolation (as opposed to shallow trench isolation [STI]), then another...
rf cmos layout
It is correct that this will reduce gate resistance. Split the gate into fingers and connect the fingers in metal, not polysilicon, as large areas of poly are more susceptible to failure during manufacture than smaller areas.
You should not need to make any physical connections in layout for the backgate of resistors or capacitors other than your usual nWell / substrate connections. I dont really understand your problem with your extracted simulation, can you ellaborate?
Added after 26 minutes:
By usual nWell /...
The B terminals in the scematic refer to the 'bulk' or 'body' connection of these devices, ie the substrate underneath them. Although capacitors and (poly) resistors do not connect to diffusion you should still connect these terminals in the schematic to whatever potential the substrate below...
rf cmos capacitor
- Use the metal with lowest capacitance to substrate (usually top metal but not always, check design manual) for signal tracks
- Try and keep parasitic resistance to a minimum by using low sheet RHO metal and keeping tracks short. This is of course where it gets tricky as...
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