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I did not exactly solve the problem in encounter. However, I solved the problem and made the layout LVS clea,n by writing a script which replaces the pin layer to drawing layer in virtuso.
I hope it helps for some of you having the same problem.
--Parsatt
Hi all,
I am attempting to import a gds file from encounter to virtusoo.
There is only one problem that some of ports are not recognized in virtuso when doing LVS.
When I digged into the layout and I discovered that the routing layer to encounter to the pin layer for some pins are too short...
Thank you so much for the advice. As you hinted by adding site definition to the lef file
SITE core_site
SYMMETRY Y ;
CLASS CORE ;
SIZE 0.409 BY 1.592 ;
END core_site
and making all the cells based on this unit size the problem is solved and the filler cells all cover the area and...
I have only three cells and these are the size Sites for them in lef file:
CELL1 SIZE 0.818 BY 1.592 :
CELL2 SIZE 0.818 BY 1.592
CELL3 SIZE 6.232 BY 1.592
should I use any optimization command in placement in encounter to take care of optimizing these spaces for later on filling?
Yes. I do agree. The thing is that the spaces between the unit cell after the encounter placement is not a digital value and it seems to feel that space you need infinite number of fillers!
Look at the example after the standard cell placement.
In this window at least you need three...
Thanks for the tip,
The thing is that I have all my cells in the design custom designed. (the filler as well).
The thing is that even after placing the fillers I get empty spaces as picture!
I have cells in my lef file as
CELL1 SIZE 0.818 BY 1.592 :
CELL2 SIZE 0.818 BY 1.592
CELL3 SIZE...
Hi All,
I plan to do a fabrication in a digital design technology for the first time( I have only experience in analog before).
When I am done with my design in encounter and attempt to import my design in virtuoso to do the claibre DRC check, I get so many errors on the NW and BP spacing...
Hi,
Currently I am designing a fully digital circuit. However, for some reason, I have to do a montecarlo analysis on the circuit. The only way I know is to do a feed the layout from encounter to cadence and do the spice on the extracted netlist.
However, it is really slow as the spice is a...
Hi all,
I have developed an OTA with verilogA but when I am prompted to run the PAC analysis in cadence(spectre) I get this error:
FATAL :/.../../OTA/veiloga/verloag.va : "Attempting to write a file that is not open. Open a file first then you can write to it.
Do you have any idea how I can...
I dont think if it is a problem as I have tried different name. I just added it in my ADE. Is there any alternative way?
Something silly is I tried to use a trick and plot the Weff from the result browser->output parameter ino->mn0->Weff, it gives a constant value and does not even notice that...
Exactly. This is the transistor width. I have run a dc sweep based on the transistor width and now I need to plot an exression which is based on this variable. When I try to plot it I ecounter with an error. (unbound variable)
Thank.
Dear all, I am trying to plot an expression in cadence which is based upon an independent variable from which the dc analysis is done.
The error keeps stating that "variable" is an unbound variable, or in other words, undefined. Is there any way to access this variable used by spectre?
I...
Dear Jimito13,
I have tried all the output files type. non works:(
It is done so quickly with the extraction that I know the real parasitic extraction is not carried out!!.
I changed the directory path to the original as well as you told but no progress.
However, by comparing the rcx.sh...
Yes you are right. But I don't think the output file type have anything with the problem and the setup directory is the place I have copied all the QRC setup files. including RCXspiceINIT P2LVSfile cap_coeff and...
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