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!^O^!
Oh~
Thank you LvW
so much~!
I'll do that!
Added after 19 minutes:
My DC feedback doesn't work.
The schematic has been attached.
LvW, tell me how to construct the DC feedback loop, please.... ^^
Hi,
I designed TYPE-3 error amplifier.
How can I ac-simulate my error amp?
At first, I used macro opamp model(with 80dB DC gain, 10kHz 1pole system) and ac-simulated.
My problem is
when input common mode voltage varys, vout(s)/vin(s) are different!
For example,
in+ = 0V
in - = 0V...
Thank you! FvM.
It's surprising to me that the second case has the same result as the first does!
I thought that V3 and V4 are not same after t=0, because transient response make some charge losses by R1 and C4.
I am studying so simple C-C and R-C circuits.
Figures attached below, I've calculated the voltage of the some nodes when the ideal switch is closed at t=0.
The initial condition is shown below.
t<0, V1=3V, V2=0V, C1=3F, C2=1F
when t>0, switch is closed and V1=V2=2.25V by charge conservasion...
I'm so sorry..
I dont know my folded cascode op amp works well because two diode connected NMOS(cascode NMOS) and PMOS(active load) may be wrong design method.
I can't know the type of active current mirror in ths folded cascode op amp.
It seems that Wilson current source is similar to this...
I have to design a folded cascode amp with TSMC 0.18um CMOS process
and I took a TSMC 0.18um spice library file yesterday.
What do I analysis ?
here is some specs of an amp.
VDD = 1.8V
VSS=0V
P = 10uW
A = 70dB
w(3dB) = 10kHz
OVR > 1.4V
ICMR > 1.5V
GBW = 30MHz
such as threshold variation...
cs stage with current source load
Hi
can anybody help me?
I can't resolve these problems
Problem1) show the large signal analysis of a common source stage with current source load
Problem2) why does a CS with current source(p59 in Prof. Razavi's book) need a feedback loop to force Vout...
ppm/'C is
for BGR
ppm/'C is defined by
maximum reference voltage - minimum reference voltage
------------------------------------------------------------------------------------ / Vref
temp(maximum reference voltage) - temp(minimum reference voltage)
Reference : D. Johns, K.Martin...
Hi, ^^
I want to design a buffer connected to the output node of preamplifier.
The output signal of preamplifier is influenced by capacitive load,
and I want to probe the output signal of preamplifier. Therefore, buffer is necessary.
1. Small input capacitance of the buffer is hoped(<100fF)...
Re: Where can i find the start-up ckt well suited for this b
Hmm..
I agree with butterfish
perhaps M16 needs not start-up ckt
If M21,M20 are on, then M28 is also, and if M24,M26 is on, then M29 also.
and then current is copied and then M16 goes to ON state.
and I have another question.
In...
Re: Where can i find the start-up ckt well suited for this b
Oh~ Thank you so much!
Do you know where that ckt is?
anyway I'll try to design the start-up rigth now~ ^^
one more time, thanks~
I designed bgr ckt
and I've heard that bgr needs a start-up ckt
Is it right?
If it is right, I have to design a start-up ckt
But I don't know how to design that
please somebody help me
where can i find the start-up ckt well suited for this bgr ckt?
thanks
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