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Recent content by PARAMSETTY DIWAKAR

  1. P

    skewedge error in drc error file

    hi every one i designed wideband low noise amplifier in that i used one inductor. i met all specifications. IN the layout i used circular type spiral inductor. It showing the error as skewedge in inductor layout (l_nwcr20k). i didnt draw the layout for the inductor i directly taken from the...
  2. P

    Post layout simulation problem

    Dear all, i did prelayout and postlayout simulation of an opamp,in prelayout simulation all transistors are working in saturation and gain is good 64 dB,but where as in post layout simulation,few transistors going to linear and gain falls to 50 dB,how can i get the transistors in saturation...
  3. P

    layers are not displaying in layout

    Dear all, we recently finished our layouts individually in two logins on linux os,while we integrating our work in one login,the layout layers of other login layout made is not visible.we checked all permissions of the folder,still layers are not displaying in cadence virtuoso layout...

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