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Design block gets removed during synthesis
Hello,
my design has a ROM memory and a Greatest Common Divisor (GCD) block. With every clock cycle the data set inside the ROM are sent to the GCD block for calculations. I am using a separate VHDL module for connecting the two blocks. During the...
Hi everyone
does anyone has the datasheet of BlueCore BC6130 ? I cant download it from the webpage cause I m a student and I dont have a company email
If anyone has it it would be very helpful if he could sent it to me.
Thanks in advance
Panos
I found my mistake. When I generated the gerb274x files I had the bottom layer both at the .sol and the .cmp files thats why the first image was like that.
Thanks for the help guys
Hi everyone ,
I just completed a PCB design and I would like some help verifying my gerber files before sending them to the manufacturer.
I used Eagle for the designing and Gerbv for the simulation. I can't see if there is any error in my design by looking at the .sol
and .cmp files. Is there...
Permute I did try what you said but when I used the size argument I got an error : can not have that operands in this context. In the IEEE.numeric_std library there are two TO_SIGNED functions and one of them does not use the size as argument;thats why I used it. Apparently it wasn't correct...
Hi
I am trying to convert a STD_LOGIC_VECTOR to an INTEGER using the TO_INTEGER function but I get the following error :IN mode Formal SIZE of TO_SIGNED with no default value must be associated with an actual value.
Whats wrong?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use...
Actually the answer was pretty simple. I did a long time ago but I forgot to reply, so I apologize. Read about instantiation in VHDL. You must connect the ports of the FFT block to another entity that you built. Be sure that you connect scale_sch_we, fwd_inv_we and start ports. The scale_sch and...
Hi ,
I want to use the FFT 7.1 logic core in Spartan3E. I did a 16QAM mapper and I want to connect it to the FFT in order to make an OFDM modulator. The problem is that the outputs of the FFT (real and imaginary) are both the same when the conversion is done. What am I missing? here is the...
FvM excuse my ignorance but I am new to VHDL and when I see timings I always think of delays, and I know that you can't have delays in your code unless its a testbench file. Moreover I have learnt that for all the synchronous functions you need a process and an if statement that checks the...
FvM I want to connect a DDS core before the SPI interface. The DDS core has a ready signal for output when the data are valid. So I want to check when this signal is ready in order to start the transmission through the SPI. I sent this data to the DAC...
FvM and TrickyDicky I tried both your ways but I don;t get the results . This the code :entity SPI is
port(clk, ALOAD : in std_logic;
D : in std_logic_vector(11 downto 0);
SO : out std_logic;
clock_out : OUT STD_LOGIC;
chip_select : OUT STD_LOGIC);
end SPI...
TrickyDicky I know that I have to use a clock. I use this ALOAD as a ready signal to know that I have data for my input. But when I run the simulations I must have a transition from '0' to '1' on the ALOAD in order for the ddata to shift. I want when ALOAD is '1' the data to be shifted and when...
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