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Hi,
1. nxtgrd files are binary files. It is get any info by opening it in a text editor.
2. Yes you are right, if the timing is closed in MIN and MAX, there is a less possibility that in TYP timing will fail.But how to know the timing of the chip in TYP condition. You will not operate every...
Hi,
In P& R when we route the nets, we will be having info about Length and width of the nets.
But we are not sure of R&C of these nets. To get these values we use the nxtgrd files with an extractor (ex:Star-RC, QRC and so on).
nxtgrd used by Star-RC. other tools use other format. These files...
Hi,
During the P&R, yes we know the length and width of the nets. But during manufacturing no body is sure, what is the length and width.
There are some variations. So the foundry release the extraction corners files and ask us to close the timing in these corners.
for 45nm, please see the...
Hi ,
>Is the PVT the Operation Condition?
Yes. This is correct
>Is the OCV the variations on a given PVT?
Yes. This is right. IT may be a process, voltage and temperature
>Is the Corner and OCV the same?
No. This is not correct. Corners are extraction corners. During fabrication, due to process...
Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?
Hi,
My point is
Approach#1: This is good for Low Frequency and low-power designs.
Approach#2: This approach is good for high frequency designs.
This will be my approach. Let us discuss some more on this.
Hi,
These are the following terms we will re-define
1. corners =extraction corners [it may vary from node to node. The number of extraction corners are defined by Foundry.]
2. checks = setup and hold [ transition, cap and fan-out will be checked anyway]
3. Derates= 1 sign-off values each for...
Hi,
the differences in the 3 models of synthesis:
Wire load model:
This models gives a vague information about R and C values for a given area and fan-out of the cells
RC-PLE:
This models needs LEF of std_cells, memories and IPs and captables of particular corner. From LEF we have the...
Hi,
While converting RTL to Gate level net-list, we will guide the tool for picking fast, less leaky cells using clock information.
That is the main reason for clocks/constraints.
Hi,
Yes of-course. some of the spacing and width rules you can change for specific nets.
You can define these in separate LEF files and read into the tools.
Do you have any specific rule to be added into the EDI?
Sorry for the confusion.
The corner i mean is operating condition. i.e max and min conditions. In max we check setup which is crucial. And in min we check hold.
std_cells will have min/max delays. But i am not sure of OCV derates
Derate values you can apply for nets also using the command...
RC extraction extracts R and C numbers of the nets based on the L and W. for this tools use R&C tables from foundry.
Where as OCV numbers are applied during STA. These are applied on the extracted circuit and timing is analysed.
Am i clear?
Hi,
The Error you are getting because of some cells which are fixed and not on placement grid.
To fix this Error
1. check_legality -verbose
2. check the cells which are overlapping or fixed and not on placement grid.
3. unfix the cells and place them on grid. Again fix them
4. If they are...
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