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I think you are well aware of the problem of using Distributed Memories.
looks like a coding issue. Is if statements are intentional?? Imagine the case when two or more write ports want to write.
Its trying to infer 1K+ flops to make this reg file...
Added after 1 hours 9 minutes:
Just to...
Xilinx ISE9.1
Yes , you can write . By the way what kind of test parameters you are going to use?
you may not get all the features of verification. But you can easyly simulate designs ( relatively small designs) in ISESim.
why can't it direct assign the GCLK pin to DCM instead?
You can connect it directly . but to do that you have to instanciate the DCM primitive in your code and connectt he pin. On the other hand if you use the architecture wizzard , it will instantiate an IBUFG in between your GCLK pin and the...
GCLK pins are the "Global clock pins" you can feed an external clock signal to FPGA using these pins , both in single ended and differential modes.
Ex. In xilinx ML555 board a 30 MHz clock input is used on GCLK pin(L19).
Once the clock signal is inside the FPGA you can used BUFG and pass it to...
As Farhad said when you write like this its like driving a fip-flop with 2 clocks.
From the look of it , what i can see is the SET signal not required to be edge sensitive.
You can try somethign like this ( it will synthesize).
if you want it to be asynchronous set then you can do something...
Can you tell me exactly what you are looking for?
Xilinx FPGAs has internal GLOBAL routing lines .
There are certain pins dedicated to connect clock ( xtal) to the FPGA. You can see those in FPGA editor . If you are using ISE11+ then use PlanAhead.
yes , you can
try something like this.
after the VSIM ....
write something like this
view wave
add wave -noupdate -format Logic -label clk /top_tb/top_DUT/CLK0_OUT
for more information on this commnad you can refer to the modelsim reference manual.
it entirely depends on the size of the array and the coding style sometime.
Block ram is the dedicated ram blocks inside the fpga.
Distributed ram is basically using those Luts,SRL16 and flops in the CLBs.
block ram can operate faster than the distributed ram.
i am bit confuged after looking at your block diagram.
Based on it i am commenting few things.
1. system generator will do the hdl sysnthesis fpr you on only the blocks you placed between "gateway in" and "gateway out". rest of all modules considered as black box.
2. the module you are...
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