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Thank you for your reply. I found in many papers the trend of background calibration is to squeeze the calibration time. So in some application requires the calibration time is short. Can you give some example of application that the background calibration is not suitable?
Do you mean that the ADC will first of all running the calibration when power-on? So when I use such ADC I should wait for a certain period for the calibration running like initializing, right? In what application such background calibration is not feasible? And in what appplication the...
Hi, guys. From many papers or book they said that the background calibration will not disturb the normal ADC operation. But the calibration operates at backgournd needs large clock cycles to complete. So does it mean that there is a great delay between the input signal of ADC and the...
I follow the theory that for a 14-bit ADC, the DC gain of THA should be larger than 100dB to remove the static error. But recently when running the trasient simulation, I found that if changing the DC gain to Av=70dB, the THA output still remains as ideal as the DC gain equals 100dB. But I was...
Here the Vcm i mean the virtual ground node of the OTA, not the input common mode signal. u can see that the Vcm connects to the bottom-plate sampling switch. Even the settling of input switches S1 is different, how does it relate to the virtual ground voltage ?
the fact is that when i equal...
I think this is the fully diff structure, the switches which connect to Vcm has the same Vds and Vgs, the settling seems to be the same. Please correct me!
Could you explain more specific why and which one is the higher and lower settling switch?
Thank you!
Can you tell me what detailed part I shall upload here?
I'm sorry, it is not the problem due to THA but first pipeline stage instead. The virtual ground node of first stage is set to Vcm. Theoretically the matching of MDAC capacitor is the main contributor to the nonlinearity. But in...
I designed a 14-bit 50Msps pipelined ADC, I used fully differential flip-around THA, and the virtual ground voltage set to Vcm as shown in the figure. If I vary Vcm, the whole accuracy of my ADC varied accordingly. But ref to the thoery, the Vcm will not affect the conversion accuracy. So...
Hi,guys
I need to design a line driver which will operate at 100Hz---2MHz,5V as Vcc and output connects to 2:1 transformer and current driving ability of 60mA as max should attained. The driver input ranges from 50mV to 4V.
Who can tell me which topology I shall use and procedures on how to...
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