Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hello sir,
that is only two warning massages on icv.log
WARNING: Unable to find the script 'rsh'.
WARNING: Unable to find program "rsh". Using "ssh" instead.
and i think that is no relations with these two massages with adding metal fill.
because in icv standalone these two warning messages...
hello all,
i am using technology TSMC 65nm and i reach to final stages, now i am trying to add metal fill to avoid min density violations.
i am using ICV (ic validator) to do this on ICC2 using command (signoff_create_metal_fill).
here is a problem, when i run this command it takes time to...
I know that,
My question is I run filling on metal layers, no thing happened.
In TSMC dummy runset, there is many switches, actually we switched on all switches we need and also there is nothing happened.
Hello all,
I want to make auto metal fill in design using ICV on ICC2.
I did everything discussed in ICC2 user manual of how to do this.
I am using TSMC 65 nm technology.
I used dummy run set as a metal fill run set.
And when I run the command to auto metal fill (signoff_create_metal_fill), it...
Hello sir,
Great thanks for your attention.
Actually, i have only a few years of experience of working.
But i opened the technology file and found that the technology name is TSMC N65 SP9M6x2z TCBN65.
So, i decided to choose runset ICVLN65S_9M_6X2Z for ICV or CLN65S_9M_6X2Z for calibre.
Is that...
Hello everyone,
I have nearly 400000 DRC errors on VIA7.
I am using technology TSMC 65nm with runset M9_6X2Z
actually, i can't understand why this errors appeared for me.
Can someone help me to understand why this errors appered?
this is a complete description of this error:
0: Layer: VIA7...
Thank you sir, and I will read surah Al waqiah ❤️ ISA.
But one thing to take into account I see in layout gui that the spacing actually is very large between Vdd and Vss.
Also I see one neighbour standard cell don't get this violation.
So, I am not sure is that actually a problem?
And also...
I face a problem, during powerplanning when I connect power and ground nets to power and ground pins, then when I check pg drc, I get a huge number of drc violations in metal 1 between vdd and vss metals.
The drc error is end of line keepout zone violations on metal1 inside standard cell.
I...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.