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Recent content by odeafeiner

  1. O

    how to do ECO for a design?

    If you want to get some idea, you can try to use altera Quartus tools to see some ECO experience.
  2. O

    regarding altera DDR2 Controller IP core

    simulate altera ddr2 controller hi, If you follow the user guild, there should be no problem. One thing you need to make sure that you don't use the DDR2 synthesis file when you do simulation. you should use xx.vo (simulation) file not xx.v (synthesis) file. I remember "auk_ddr_controller"...
  3. O

    regarding altera DDR2 Controller IP core

    can controller ip core did you include the path of altera ddr2 ip library?
  4. O

    Altera DDR2 Controller Core

    hi, I don't think there is special thing. I also use micron model though our board use different. you should set the board related timing when you generate IP (I also tune them in the board test). The thing I though is that the clock setting is same with your IP setting. the read latency is...
  5. O

    Altera DDR2 Controller Core

    we did it both with simulation and in the board. megawizard have one testbench. just run as it said.
  6. O

    timing is meet, but function is not right

    hi, I have a design with Quartus tools 6.1. The timing is meet by timing analysis report. But the function is not right with some modules. These modules are instanced with same code. (the other module function is good). Of course the function simulation is passed. The difference I can see now...
  7. O

    Looking for info on flash memory controller

    memory controller search xilinx or altera
  8. O

    using of perl with verilog

    www.doulos.com for perl part
  9. O

    What's the best text editor for Solaris for Verilog coding?

    best solaris text editor EMACS with verilog mode is a good choice.
  10. O

    XML file for verification/eda

    hi, Does anybody have some experience with XML file in the function verification or eda field? I want to know how XML do in such field, data exchange ...? Thanks,
  11. O

    Looking for materials on die size estimation in digital core

    Re: die size estimation yes. It will be different between pad-limited and core limited. And if you use UMC technology, i remember that they have such tools in the web also.
  12. O

    how to deal the path who can't satisfy timing constraints?

    check the timing report first. If the period constraints violation is small, try use more powerful synthesis option. otherwise try to modify the rtl code. For the offset constraints violation, check if you register in/out the io register. I remember ISE has build-in timing analysis tools...
  13. O

    SPI-3 PHY layer implementation-- NEED help!

    looks like there is no spi3 implementation in opencores.org
  14. O

    what is COT(Customer owned tooling)

    hi, Just like the name means, COT(Customer owned tooling). The tools are developed by customer themselves, not by the famous EDA vendor, such as Cadence, SYNOPSYS, and mentor ..... You cannot got detail information about these tools if you are not in the company. IBM, Intel, and even some...
  15. O

    How choose wireload models for synthesis ?

    hi, You'd better check the datasheet from your backend vendor(library supplier) for accurate wireload models settting. But people said there is no needed wireload models with advanced physical synthesis tools. no experience with this. regards,
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