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Recent content by oak_tree

  1. O

    [SOLVED] Signed multiplier in Verilog. "signed" doesn't work

    Re: Signed multiplier in Verilog. "signed" doesn't work Thanks Shibin. It worked, but I needed to add () in order not to get a compliation error: assign multout = dccfltro * $signed ({1'b0, one_a});
  2. O

    [SOLVED] Signed multiplier in Verilog. "signed" doesn't work

    Thanks for the replies. I had 'signed' also for one_a. However, what prevented it from working is {1'b0, one_a} (the 0 in front). What I did after reading the replies is define one_a as "signed [8:0]", and then drove 0 for the MSB in the instantiation. That works. Thanks again for all the...
  3. O

    [SOLVED] Signed multiplier in Verilog. "signed" doesn't work

    Hi, I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me. Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get...
  4. O

    Post synthesis timing issues

    The thing is that with multiple clocks and clock gating, prelayout simulations as it was described by Hung (zero delays, no timing checks, etc) don't work most of the time. You can try that, but you may want to wait till you have SDF and clean timing.
  5. O

    Post synthesis timing issues

    Hung wrote everything you need to do. SDF includes the timing of all timing arcs. If you'd like to run gate level simulations, you should make sure your timing (STA) is clean. If you don't have SDF or the timing is not clean, then you shouldn't use any delays.
  6. O

    Isolation cells (hold recent value?)

    Hi all, In some reference books it is mentioned that there are 3 types of isolation cells: Those that clamp the signal to '0', those that clamp the signal to '1' and those that latch it to the most recent value. We are using 65nm TSMC library, low power (tcbn65lphvt). I can see just the...
  7. O

    clock multiplexer problem - help needed

    clock multiplexer I don't think you need to. STA tools know to analyze both clocks. You'll get 2 paths.
  8. O

    What are the guidelines that we use while doing floorplan?

    Floorplan GuideLines Mainly where to place the macros. For example, if you have cores that access memories, you want all the same type (for example, IRAMs for an ARM core, or PRAMs/XRAMs/YRAMs for a DSP core) to be in one area of the chip. In addition, you may want to create regions (e.g., PLL...
  9. O

    Multi voltage and multi power mode design partitioning

    Thanks for the answer. What I meant is that I have currently one module ('A'). Let's say that I have a state machine that I'd like to put on 'always-on' power domain, and I'd like to shut off the power to the rest of the logic in that module. Do I have to create a new module ('B'. Module B is...
  10. O

    Multi voltage and multi power mode design partitioning

    Our next chip is going to be in 65 nm. That's a big jump from 180 nm. I'm not too familar with the flow, and I'll appreciate any input. My first question is in the RTL level. I know that UPF/CPF is used to assign a voltage and power mode to each module. What if an exixting module contains some...
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