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Hi MFahmy,
Thanks for your reply! Yes, I am still interested in that paper.
N.X.
---------- Post added 16-02-12 at 00:01 ---------- Previous post was 15-02-12 at 23:13 ----------
Hi MFalmy,
You can send the paper to xingnw@yahoo.com. I real appreciate your help!
Thanks!
N.X
Hi I am looking for a paper:
A CMOS complex Gm — C filter for low-IF bluetooth receiver.
by:Fahmy, M.M. Mahmoud, S.A.
it's appear on Microelectronics, 2008. ICM 2008. International Conference on
Thanks
NX
Hello
I have a basic question regarding switched-capacitor integrator circuit, look at the attached drawing (from Paul Gray's book, chapter 6). on the top phase (sample phase), I am wondering what's the charge at right plate of C1? I am thinking because it's connected to ground (or any DC...
Hi,
I need to design a divider to divide the signal by 2.5 ( the input signals are at around 4GHz), I would prefer the injection lock divider. Does anybody have any idea how to design that? or can refer to any papers regarding this matter?
Thanks
Norman
Hi,
I am trying to study the version sync with Cadence, but can not find any documents either online or with Cadence. Can anybody give me a hint where I can find them?
Thanks,
nxing
Hello everyone,
I have an differential LNA and would like to measure it's PSRR. what I am thinking is that the measuring of a "pseudo single-ended LNA" 's PSRR make more sense. Does anybody can tell me how to set the test bench up?
Thanks
nxing
LNA input impedance
Hi Khouly,
Sorry, the stability factor is actually less than one, indicating unstability. I just wondering what is the cause of this unstability, what I found is that if I lower the OUTPUT inductor's Q, the stability factor increased. Also I found that the Cgs of this...
LNA input impedance
Thanks for the reply, guys.
For Yakeen:
I don't see any problem with Vg, also, this is not a close loop.
For Khouly:
Actually, I check the stability factor and it's larger than 1 everywhere.
Any other suggestions?
Thanks
LNA input impedance
Hello everybody,
I have a CMOS LNA and the topology is the classic cascode architecture with inductor degeneration at source of input device. what I find is that I can see a negative Z11 (real part) after the S-parameter analysis. Have anybody met the same problem? how come...
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