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1/10 rule is for integer PLL, for fractional-N, the ratio needs to be much higher, e.g. 10MHz reference with 100KHz loop filter bandwidth, but it can still offer you fine resolution, such as 10Hz, of course can be 200KHz too.
what is shielding in analog layout
if you use the ptap on a p-substrate, you must connect to VSS, if you use NWELL and ntap(which make the size bigger) as guard ring, it must be connected to VDD.
if it's metal, yeah, I agree that the VSS is uaually more stable and available.
lvt hvt
usually you can first synthesis with only the low Vt cells, then optimize it, it will replace some of the non-critical cells with high Vt cells so that it can reduce the leakage power, and meet the timing requirement at the same time.
In the cmos rf circuits, we have a stacked design, if I want to connect the bulk for upper nmos transistors to a higher voltage instead of gnd, what's the best way of connecting them in the layout? should I use a dnw+pwell?
thanks in advance.
it's confusing, sometimes we talk about saturation mode, for the amplifier, it's non-linear for the signal, for the cmos transister, it's the normal working area instead of going into triode region, so need to be clarified.
I have one of this question too, if we want to reduce the resistance of the poly, can we connect it to the M1 with vias directly, that means the M1 will be routed directly above the poly for gate.
I installed the neocell under both linux and solaris, but I could not find the neocell setup wizard in the neocell menu, does anybody know where is it?
thanks in advance,
nozone
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