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Dear All,
I am working with a finfet based PDK and noticed that there are two options available for the high-R resistor: 2 terminal or 3 terminal. In my understanding, there should be no difference between the two since high R is by itself a thin film based resistor and therefore the body...
Dear All,
I am working on a reliability test chip and need to stress devices way higher than normal. The chip is all about stressing devices and sensing voltages. The nominal domain (consisting of shift register, etc) has a good amount of decaps but I am considering not to add any decaps to the...
Thank you for your responses !
As you correctly pointed out, LVS was, infact not completely clean. LVS passed with stamping conflicts and ERC did not pass. I ran LVS again and verified the ERC error: 'ptap connected to VDD'
Dear All,
Recently, we encountered an issue in one of our chips where someone accidentally connected a psub guard ring to VDD instead of GND. Post chip tapeout we noticed heavy leakage current whenever input voltage was given to the pad in which the guard ring was connected with the opposite...
Re: Guard Ring / Well Tie for a dc test circuit
Thanks for the response !
Still looking for answers to qs 2 and 3. Just to clarify, although the core transistors have no guard rings, as you correctly pointed out, the purpose of putting a single guard ring at the intersection of the two VDD...
Dear All,
I am designing a circuit for dc stress characterization of an array of transistors. I have two voltage domains in this circuit sharing a common ground (Stress Voltage and Nominal Voltage). The stress voltage comes from a bare pad whereas nominal voltages are esd protected. Testing...
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