Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by nivico

  1. N

    problem ON ANALOG CMOS circuit!

    thnaks for your advice , it is true that i am a begginer,i also see the enhancement , i will go on ;i just posted the first stage of an amp . i can easily get the bias "v9 N3 vss 3" , i think the other transistor suply a voltage rather than copy the current as the ransistor can be different...
  2. N

    problem ON ANALOG CMOS circuit!

    It costs to use Cadence,thanks a lot for your reply.during the time, I did much simulation,and got a much better result,the CMRR is 81dB,and 3dB frequence is about 3Mhz ,here is the spice file.we can have more discuse on this topic. Added after 52 seconds: * SPICE netlist written by S-Edit...
  3. N

    problem ON ANALOG CMOS circuit!

    mcnc 1.25um cmos parameters Here is the t-spice file I just simulated,it is about a differencial amp.please help me check the file,or adjust the paramenter,thanks a lot! * SPICE netlist written by S-Edit Win32 8.10 * Written on May 29, 2005 at 22:32:21 .include...
  4. N

    problem ON ANALOG CMOS circuit!

    min w 1.2u cmos I am a university student from China. I am doing some design of cmos analog opamp using TANNER EDA,and was confused by the W/L;I am using orbtn12/orbtp12 tech. i appreciate your help that you could send me a finished design of a simple design, t-spice file,layout even better...

Part and Inventory Search

Back
Top