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Its like when rising edge of '1' bit data I am shifting 1 for 8 times and falling edge of '1' data bit I am shifting 0 here .
So in total 16 cycles output of 8 bit vector .
Basically a 1 bit is divided into 16cycles of 8 bit vector . So want to know the clock for this 8 bit vector generated ?
Eg if 1 bit generated in Tbit clock
then is (Tbit clock/16) is the clock of 8 bit vector generated ?
let me know an I making sense now
Thanks
Hi ,
I am generating one bit data (Manchester code ) at Tclock period.
This 1 bit data is sent in 16 cycles in 8 parallel bit format . Basically a shifting 1 for rising edge and 0 for falling edge
eg . 1000000 1100000 11100000 ...................... 10000000 11100000
what should be the...
HI,
I need to code Manchester encoder - decoder . I am very new to this .
Can any one provide the Manchester encoder and decoder code in VHDL please .
Thanks in advance !
Niraj
Yes I want to have model out of analog block .
So in this case does all the behavioral model for analog blocks are hand coded ones
?
Thanks for your reply ,
Hi ,
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Hi , I need some good documents about implementation of Elastic buffer / 8b/10b encoder - decoder . It will be great if you could point me to relevant stuffs of these topics.
Thanks in advance , Niraj
could anyone please specify the digital diagram to derive the clock of 33MHz from 50MHz input. Basically would like to know clock divider circuit for this .
Thanks , Niraj
Hello there,
consider a design which works for certain frequency of ex 100 Mhz and I have been asked to target this to 200MHz . From design/coding perspective would like to know best ways to increase the performance of speed of operation in terms of architecture , RTL coding apart from...
HI
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