Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have designed a 16-bit modified radix-4 booth multiplier in cadence and simulated it using ADE (Analog Design Environment).
I wonder if there is any automatic method to calculate the worst case propagation delay of this circuit or I have to use a brute force method to find it?
As a matter of...
Hello everybody
As a matter of fact, I'm new to cadence virtuoso and usually use gpdk180 library to simulate schematics in cadence using ADE (analog design environment). But when I was looking around in my Linux machine, I found a folder named SC_TSMC180 beside my gpdk180 folder and wondered...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
