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Clock nets r highly switching nets and needs less delay to reduce the skew,slew etc...
high metal layers have less resistance and in order to reduce the crosstalk we use shielding or isolation
though a blocking statement in always with posedge clk sttement always infers Flip-Flopo only.A latch with posedge senistivity is not possible.correct me if i am wrong...
always @(posedge clk)
begin
q <= p;
p <= d;
end
always @(posedge clk)
begin
p <= d;
q <= p;
end
how this works?does it give any error???
Added after 2 minutes:
two always blocks in a single module will be execued parallaly.right???
u wl get a synthesized verilog netlist after synthesis with .v extension
u need this .v netlist and verilog models of ur technology library to do the post synthesys simulation.u can do this simulation in any smulator like modelsim,NC,VCS...etc
frst u compile the verilog models of technology...
vhdl code
sounds like an assignment question.i cant write whole code,but i can give some hints
use case statrement for 4 modes.inside each case u simply count the counter.
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