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Hi, I am design logic library in cadence, for multiplexer Y = S*D0 + (S')*D1, there are 2 structures to implement in the picture, which one should I choose ? Does it affect to signal strength when we use pass gate or tranmission gate to design logic circuit ?
I'm design a digital PDK library using cadence. For basic gate such as not, nand, nor,... I draw schematic in transistor level using nmos and pmos. But for bigger IC like full-adder, DFF,... Can I draw it using basics gate that I drew above or draw completely in transistor level.
I was stuck with multiplier ? please help me
In floating point multiplication, when we multiply the mantissa, we have to add bit-1 on the left of mantissa to make a 24-bit binary. But if I do that and using Booth algorithm, It'll be wrong because the booth algorithm works with signed number. We...
I design a floating point multiplication. After multiplying the mantissa of multiplicand and multiplier is the normalize step. I need to detect the first bit 1 from left to right of a 48-bit series.
For example:
01 01010110000000000000000 0000000000000000000000
from left to right, i detect bit...
I am designing a multiplier circuit using Modified Booth Algorithm, I examine group of 3 bit to generate a partial product, so I have total 13 partial product. The product will be 48 bits. I'm stuck at the sum circuit. My idea is to use 48bit Carry Lookahead adder to sum al partial product but...
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