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Recent content by nelsonys

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    Problem with modeling of HFSS (Correlation between HFSS, SIwave and Measurement)

    Thank you Sir for your advice. You mean for such an uneven distribution of dielectric and metals, it is not possible to force the lumped port to excite TEM right? Yes you are right Sir. Those holes are supposed for SMA connector for S-parameter measurement use. Let me try if could import a...
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    Problem with modeling of HFSS (Correlation between HFSS, SIwave and Measurement)

    Hi PlanarMetamaterials, Thank you very much for your insights! So for this case, which if I need to create lumped port across Signal via and Ground via, do you think it is possible to excite the proper mode? I've tried hard to comprehend your insights and had a check on those ports. I think...
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    Problem with modeling of HFSS (Correlation between HFSS, SIwave and Measurement)

    Hi PlanarMetamaterials, Thank you so much for letting me know my stupid mistakes as I have no idea on how to create a good lumped port. For this case, it is a round via and I have no idea how could I create a sheet without overlapping the conductor. Forgive me as I am an absolute newbie. For...
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    Problem with modeling of HFSS (Correlation between HFSS, SIwave and Measurement)

    I am trying to model HFSS in order to get good agreement with the measurement results. As we know, SIwave has its own method of forcing the boundary condition to maintain the TEM mode of the pcb, and it saves a lot of times and technical issues by giving a highly accurate simulation results for...
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    Study about Resonance

    Thank you for the link. What I really hope to know is how to relate VSWR, half-wavelength to resonance. Their relationship is kind of vague to me. Appreciate a lot if anyone could enlighten me on this. Thanks.
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    Study about Resonance

    I am now studying about resonance on transmission line. Is there any recommendation on good study materials (books or any online materials) about the mechanism of resonance and the relationship between reflection (standing wave) as well as lambda/2? Further topics about resonance such as...
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    Calculating Length-matching requirement for DDR2

    Thanks Loosemoose and Buenos... I just don't have the concept of calculating the skew budget for DDR2 board trace. Instead of considering flight time, it seems like we need to take into consideration of setup and hold time according to Intel's note. ---------- Post added at 17:44 ----------...
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    Calculating Length-matching requirement for DDR2

    According to i.MX53 datasheet, we have to route Add, Data and Control signals within +/- 25mils of the length of the clock for the correct latching. I wonder how can we calculate out this value. and how do we implement it? Say we route clock signals first and get the largest possible length of...
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    Stack-up of a six-layer help

    fpga-developer, Did you consider the crosstalk in between L3 and L4 signals? I wonder why Intel routed PCIe signals in between these layers too...
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    BGA Breakout routing for impedance-controlled board

    Thanks both Marce and FvM! I came across a book from Intel that for PCIe, they did not explicitly required a certain impedance for the trace, and they mentioned as long as the differential trace stay in 100ohm +- 20%, it would give correct outcome. Forgive me for my ignorant, isn't this...
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    BGA Breakout routing for impedance-controlled board

    I have come across Intel board design which is designed in a rather confusing way. Sorry it's a classified document which I'm not able to show it here and I'll try my best to explain in words. The PCB designers of Intel squeezed 4-5 traces in between breakout pins from BGA. These traces need...
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    Routing signals on the inner layer under crystal oscillator or switching regulator

    Marce, Yes I have rules for not routing any signals under switching power supply, but for prototype version, we are constrained so much by the board size set by the circuit designer. And this is one of the communication gap between them. Besides, I'm quite confused with we don't any ground...
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    Routing signals on the inner layer under crystal oscillator or switching regulator

    Marce, Any documents to support this? Circuit designers need proofs for this...
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    Is my layout good enough for a Mixed signal design.

    hallovpin 1. Power supply should be placed near digital circuits, otherwise the return path of digital circuit might pollute the analog circuit return path inadvertently. 2. You have to check the pinout and datasheet of your ADC carefully and refer to their decoupling advice. Ferrite bead is...
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    Routing signals on the inner layer under crystal oscillator or switching regulator

    I have a board space constraint with my current PCB. I am thinking of routing some signals under the crystal oscillator and switching regulator on the inner layer. I was wondering how severe will the effect be? As far as I've learnt, noise coming out from crystal oscillator and switching...
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